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    VERTICAL GATE TRANSISTOR AND PIXEL STRUCTURE COMPRISING SUCH A TRANSISTOR
    461.
    发明申请
    VERTICAL GATE TRANSISTOR AND PIXEL STRUCTURE COMPRISING SUCH A TRANSISTOR 有权
    垂直栅极晶体管和包含这种晶体管的像素结构

    公开(公告)号：US20150279883A1

    公开(公告)日：2015-10-01

    申请号：US14660847

    申请日：2015-03-17

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Jean-Robert MANOUVRIER ,  Pascal FONTENEAU ,  Xavier MONTAGNER

    IPC: H01L27/146 ,  H01L29/423

    CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

    Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

    Abstract translation: 本发明涉及一种光电二极管，包括：P导电型衬底区域，用于收集当衬底区域的后表面接收光时出现的电荷的电荷收集区域，所述收集区域包括形成深的N导电类型区域 在基板区域中，形成在基板区域中的N导电型读取区域和隔离的转移栅极，形成在与N导电型区域的侧面相反延伸的深隔离沟槽中的基板区域中， 并且被布置为接收栅极电压以将存储在收集区域中的电荷转移到读取区域。

    METHOD FOR PROTECTING A PROGRAM CODE, CORRESPONDING SYSTEM AND PROCESSOR
    463.
    发明申请
    METHOD FOR PROTECTING A PROGRAM CODE, CORRESPONDING SYSTEM AND PROCESSOR 审中-公开
    保护程序代码，对应系统和处理器的方法

    公开(公告)号：US20150220456A1

    公开(公告)日：2015-08-06

    申请号：US14610924

    申请日：2015-01-30

    Applicant: STMicroelectronics SA

    Inventor： Bruno Fel

    IPC: G06F12/14 ,  G06F12/08

    CPC classification number: G06F12/1408 ,  G06F12/0802 ,  G06F21/125 ,  G06F2212/1052 ,  G06F2212/603

    Abstract: Program code intended to be copied into the cache memory of a microprocessor is transferred encrypted between the random-access memory and the processor, and the decryption is carried out at the level of the cache memory. A checksum may be inserted into the cache lines in order to allow integrity verification, and this checksum is then replaced with a specific instruction before delivery of an instruction word to the central unit of the microprocessor.

    Abstract translation: 旨在复制到微处理器的高速缓冲存储器中的程序代码在随机存取存储器和处理器之间被加密传送，并且在高速缓冲存储器的级别执行解密。 可以将校验和插入到高速缓存行中以便允许完整性验证，然后在将指令字发送到微处理器的中央单元之前，该校验和被替换为特定指令。

    METHOD FOR PRODUCING A CAPACITOR
    464.
    发明申请
    METHOD FOR PRODUCING A CAPACITOR 有权
    生产电容器的方法

    公开(公告)号：US20150206662A1

    公开(公告)日：2015-07-23

    申请号：US14416978

    申请日：2013-07-12

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

    Inventor： Yann Lamy ,  Olivier Guiller ,  Sylvain Joblot

    IPC: H01G4/30 ,  H05K1/18

    CPC classification number: H01G4/306 ,  H01G4/33 ,  H01G4/38 ,  H01L28/87 ,  H01L28/91 ,  H05K1/181

    Abstract: A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

    Abstract translation: 一种用于在基板的一部分中制造电容器堆叠的方法，所述方法包括：从所述基板的上表面沿着所述基板的所述部分的厚度形成空腔，将有助于所述电容器堆叠的多个层沉积到所述基板上 空腔的壁和上表面上，并且从层中去除物质直到达到上表面的表面。 腔的形成包括形成至少一个沟槽，并且与每个沟槽相关联，至少一个盒子。 至少一个沟槽包括通向盒子的沟槽出口。 盒子包括在上表面开口的盒子出口，盒子出口的形状大于沟槽出口。

    HETEROJUNCTION BIPOLAR TRANSISTOR RELIABILITY SIMULATION METHOD
    467.
    发明申请
    HETEROJUNCTION BIPOLAR TRANSISTOR RELIABILITY SIMULATION METHOD 审中-公开
    异相双极晶体管可靠性仿真方法

    公开(公告)号：US20150142410A1

    公开(公告)日：2015-05-21

    申请号：US14541627

    申请日：2014-11-14

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Salim Ighilahriz ,  Florian Cacho ,  Vincent Huard

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

    Abstract: A method of circuit simulation includes: simulating, by a processing device, behavior of a heterojunction bipolar transistor device based on at least a first base-emitter voltage of the transistor to determine a first base or collector current density of the HBT device; and determining whether the application of the first base-emitter voltage to the HBT device will result in base current degradation by performing a first comparison of the first current density with a first current density limit.

    Abstract translation: 一种电路仿真的方法包括：通过处理器件模拟基于晶体管的至少第一基极 - 发射极电压的异质结双极晶体管器件的行为，以确定HBT器件的第一基极或集电极电流密度; 以及通过执行所述第一电流密度与第一电流密度极限的第一比较来确定是否将所述第一基极 - 发射极电压施加到所述HBT器件将导致基极电流劣化。

    METHOD OF FORMING STRESSED SOI LAYER
    469.
    发明申请
    METHOD OF FORMING STRESSED SOI LAYER 有权
    形成应力SOI层的方法

    公开(公告)号：US20150118824A1

    公开(公告)日：2015-04-30

    申请号：US14526005

    申请日：2014-10-28

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

    Inventor： Denis Rideau ,  Emmanuel Josse ,  Olivier Nier

    IPC: H01L21/762 ,  H01L29/78 ,  H01L21/02

    CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/324 ,  H01L21/76237 ,  H01L21/84 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7847

    Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.

    Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。

    METHOD OF STRESSING A SEMICONDUCTOR LAYER
    470.
    发明申请
    METHOD OF STRESSING A SEMICONDUCTOR LAYER 有权
    压电半导体层的方法

    公开(公告)号：US20150118823A1

    公开(公告)日：2015-04-30

    申请号：US14526053

    申请日：2014-10-28

    Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

    Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

    IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

    Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

    Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。

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