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    Method of forming split gate memory cells with 5 volt logic devices
    461.
    发明授权
    Method of forming split gate memory cells with 5 volt logic devices 有权
    用5伏逻辑器件形成分离栅极存储单元的方法

    公开(公告)号：US09570592B2

    公开(公告)日：2017-02-14

    申请号：US15164796

    申请日：2016-05-25

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Vipin Tiwari

    IPC: H01L21/28 ,  H01L21/265 ,  H01L21/768 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11529 ,  H01L29/66484 ,  H01L29/7885

    Abstract: A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.

    Abstract translation: 在具有存储区域（具有浮动和控制栅极）的第一逻辑区域（具有第一逻辑门）和第二逻辑区域（具有第二逻辑门）的半导体衬底上形成存储器件的方法。 第一注入形成与存储区域中的浮置栅极相邻的源极区域，以及与第一逻辑区域中的第一逻辑门极相邻的源区域和漏极区域。 第二注入形成与第二逻辑区域中的第二逻辑门相邻的源区和漏区。 第三注入形成与存储器区域中的控制栅极相邻的漏极区域，并且增强第一逻辑区域中的存储区域和源极/漏极区域中的源极区域。 第四次注入增强了第二逻辑区域中的源极/漏极区域。

    Method of forming a self-aligned stack gate structure for use in a non-volatile memory array
    462.
    发明授权
    Method of forming a self-aligned stack gate structure for use in a non-volatile memory array 有权
    形成用于非易失性存储器阵列的自对准堆叠栅极结构的方法

    公开(公告)号：US09570581B2

    公开(公告)日：2017-02-14

    申请号：US15091202

    申请日：2016-04-05

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Willem-Jan Toren ,  Xian Liu ,  Gerhard Metzger-Brueckl ,  Nhan Do ,  Stephan Wege ,  Nadia Miridi ,  Chieng-Sheng Su ,  Cecile Bernardi ,  Liz Cuevas ,  Florence Guyot ,  Yueh-Hsin Chen ,  Henry Om'mani ,  Mandana Tadayoni

    IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/762

    CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

    Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

    Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。

    Flash memory system using memory cell as source line pull down circuit
    463.
    发明授权
    Flash memory system using memory cell as source line pull down circuit 有权
    闪存系统使用存储单元作为源极线下拉电路

    公开(公告)号：US09564238B1

    公开(公告)日：2017-02-07

    申请号：US14919005

    申请日：2015-10-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Ning Bai ,  Hieu Van Tran ,  Qing Rao ,  Parviz Ghazavi ,  Kai Man Yue

    IPC: G11C16/28 ,  G11C16/14

    CPC classification number: G11C16/28 ,  G11C7/14 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C2216/04

    Abstract: The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

    Abstract translation: 本发明涉及使用虚拟存储单元作为源极线下拉电路的闪速存储器件。 在一个实施例中，当存储器单元处于读取模式或擦除模式时，其源极线通过虚拟存储器单元的位线耦合到地，而虚拟存储器单元进一步耦合到地。 当存储器单元处于编程模式时，虚拟存储单元的位线被耦合到禁止电压，这使得虚拟存储单元处于将虚拟存储单元维持为擦除状态的程序禁止模式。

    Method of making embedded memory device with silicon-on-insulator substrate
    467.
    发明授权
    Method of making embedded memory device with silicon-on-insulator substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US09431407B2

    公开(公告)日：2016-08-30

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L21/00 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/28 ,  H01L27/12

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Non-volatile memory program algorithm device and method
    468.
    发明授权
    Non-volatile memory program algorithm device and method 有权
    非易失性存储器程序算法的设备和方法

    公开(公告)号：US09431126B2

    公开(公告)日：2016-08-30

    申请号：US14214097

    申请日：2014-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Xian Liu ,  James Cheng ,  Dmitry Bavinov ,  Alexander Kotov ,  Jong-Won Yoo

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10

    CPC classification number: G11C16/3486 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

    Abstract: A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold.

    Abstract translation: 一种用于使用编程电压的重复脉冲编程单元的非易失性存储器件和方法，具有交错读取操作以确定读取电流的电平，直到达到期望的编程状态。 每个连续的编程脉冲具有相对于先前脉冲增加阶跃值的一个或多个编程电压。 对于单级单元类型，在达到第一读取电流阈值之后，每个单元从编程脉冲中单独地移除，并且此后的一个或多个猝发脉冲的步长值增加。 对于多级单元类型，步长值在其中一个单元达到第一读取电流阈值后下降，一些单元在达到第二读取电流阈值之后单独地从编程脉冲中移除，而其他单元在编程脉冲之后被单独从编程脉冲中移除 达到第三个读取电流阈值。

    Mixed voltage non-volatile memory integrated circuit with power saving
    470.
    发明授权
    Mixed voltage non-volatile memory integrated circuit with power saving 有权
    混合电压非易失性存储器集成电路，省电

    公开(公告)号：US09378838B2

    公开(公告)日：2016-06-28

    申请号：US14257335

    申请日：2014-04-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC: G11C16/04 ,  G11C16/30 ,  G11C5/14 ,  G11C16/08 ,  G11C11/56

    CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    Abstract: An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. The voltage regulator is enabled by a controller.

    Abstract translation: 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压，并由接收第一电压的电压调节器产生。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 电压调节器由控制器使能。

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