公开(公告)号：US20240332322A1

公开(公告)日：2024-10-03

申请号：US18129407

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Kripa Chauhan

IPC: H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66 ,  H01L29/772

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66409 ,  H01L29/772

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. A first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.

公开(公告)号：US20240332193A1

公开(公告)日：2024-10-03

申请号：US18192804

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Sujit Sharan

IPC: H01L23/538

CPC classification number: H01L23/5381 ,  H01L23/5386

Abstract: In one embodiment, an interconnect bridge circuitry includes a first set of bridge-to-die electrical connectors in a first region of the circuitry, a second set of bridge-to-die electrical connectors in a second region of the circuitry, and an interconnection between a bridge-to-die connector of the first set and a bridge-to-die connector of the second set. The interconnection is in a third region of the circuitry between the first region and the second region, and includes a first trace connected to the bridge-to-die electrical connector of the first set, a second trace connected to the bridge-to-die electrical connector of the second set, the second trace parallel with the first trace, and a third trace connected between the first trace and the second trace.

公开(公告)号：US20240332175A1

公开(公告)日：2024-10-03

申请号：US18129400

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Ehren MANNEBACH ,  Mauro J. KOBRINSKY

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming backside contacts on a transistor structure by forming, during front-side processing, trenches through the transistor structure into a silicon wafer, and then, using a catalytic oxidant material that is subsequently removed, forming an oxide structure in the silicon wafer around the trenches to isolate the backside gate contact from the source/drain trenches. Other embodiments may be described and/or claimed.

公开(公告)号：US20240332172A1

公开(公告)日：2024-10-03

申请号：US18129872

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Makram ABD El QADER

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/785

Abstract: Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.

公开(公告)号：US20240332166A1

公开(公告)日：2024-10-03

申请号：US18129873

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Seda CEKLI ,  Sudipto NASKAR ,  Ananya DUTTA ,  Supanee SUKRITTANON ,  Akshit PEER ,  Navneethakrishnan SALIVATI ,  Jeffery BIELEFELD ,  Makram ABD EL QADER ,  Mauro J. KOBRINSKY ,  Sachin VAIDYA

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295

Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.

公开(公告)号：US20240332112A1

公开(公告)日：2024-10-03

申请号：US18744108

申请日：2024-06-14

Applicant: Intel Corporation

Inventor： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC: H01L23/36 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488

CPC classification number: H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US20240332077A1

公开(公告)日：2024-10-03

申请号：US18126851

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Shaun MILLS ,  Ehren MANNEBACH ,  Mauro J. KOBRINSKY

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/785

Abstract: Integrated circuit structures having backside gate connection are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive gate-to-contact connection is vertically beneath the epitaxial source or drain structure and vertically beneath and in electrical contact with the gate stack.

公开(公告)号：US20240332064A1

公开(公告)日：2024-10-03

申请号：US18126702

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L21/76808 ,  H01L21/76804 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. In particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20240331083A1

公开(公告)日：2024-10-03

申请号：US18193991

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Ronald Tadao Azuma ,  Horst Werner Haussecker

IPC: G06T3/00 ,  G06F3/01 ,  G06F3/0346 ,  G06T19/00 ,  H04L65/1089 ,  H04L65/80

CPC classification number: G06T3/16 ,  G06F3/011 ,  G06F3/0346 ,  G06T19/003 ,  H04L65/1089 ,  H04L65/80

Abstract: Methods, systems, apparatus, and articles of manufacture to produce immersive videos are disclosed. An example apparatus includes programmable circuitry to access a first video stream corresponding to a scene, the first video stream including a first video frame, the first video frame including a first tile representative of the scene from a first viewpoint and a second tile representative of the scene from a second viewpoint different from the first viewpoint, access a second video stream corresponding to the scene, the first video stream including a second video frame, the second video frame including a third tile representative of the scene from a third viewpoint and a fourth tile representative of the scene from a fourth viewpoint different from the third viewpoint, and select at least one of the first tile, the second tile, the third tile, or the fourth tile for presentation by a device.

公开(公告)号：US20240330559A1

公开(公告)日：2024-10-03

申请号：US18194237

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Raghavendra Vasappanavara ,  Srinivasa R Stg ,  Narendra Nimmagadda ,  Fadi Aboud

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to group design stages in design space optimization of semiconductor design for tool agnostic design flows. An example apparatus is to parse a file to identify a first design stage and a second design stage of a design flow, the first design stage and the second design stage corresponding to a class of design stages. Additionally, the example apparatus is to generate, based on a dictionary file, a group of operations to perform the first design stage and the second design stage, the dictionary file associated with the first design stage and the second design stage. The example apparatus is also to generate adjusted parameters for experimenting on the class of design stages, the adjusted parameters based on the group of operations. Additionally, the example apparatus is to generate instructions based on the group of operations and the adjusted parameters.