公开(公告)号：US20190149105A1

公开(公告)日：2019-05-16

申请号：US16159281

申请日：2018-10-12

Applicant: Avnera Corporation

Inventor： Ali Hadiashar ,  Wai Laing Lee

IPC: H03F3/183 ,  H03F3/68 ,  H03F1/26 ,  H03F3/187 ,  H03F3/45

CPC classification number: H03F3/183 ,  H03F1/26 ,  H03F3/187 ,  H03F3/45475 ,  H03F3/45941 ,  H03F3/45968 ,  H03F3/68 ,  H03F2200/03 ,  H03F2200/372 ,  H03F2203/45418 ,  H03F2203/45522 ,  H03F2203/45531

Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

公开(公告)号：US20190140816A1

公开(公告)日：2019-05-09

申请号：US16049474

申请日：2018-07-30

Applicant: AVNERA CORPORATION

Inventor： Samuel J. Peters, II ,  Eric P. Etheridge ,  Victor Lee Hansen ,  Alexander C. Stange

IPC: H04L7/033 ,  H04L7/02 ,  G06F13/42 ,  H04L7/00

CPC classification number: H04L7/033 ,  G06F13/4295 ,  H04L7/0029 ,  H04L7/02

Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.

公开(公告)号：US20190043469A1

公开(公告)日：2019-02-07

申请号：US16154526

申请日：2018-10-08

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Lang Lee ,  Jianping Wen

IPC: G10K11/178

Abstract: A method of adaptive noise cancellation can include receiving an audio input signal, receiving an ambient signal through a microphone, modifying filter parameters of a noise filter based on the ambient signal, and filtering the audio input signal based on the modified filter parameters.

公开(公告)号：US10200776B2

公开(公告)日：2019-02-05

申请号：US15984068

申请日：2018-05-18

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Shankar Rathoud ,  Mike Wurtz ,  Eric Etheridge ,  Eric Sorensen

IPC: H04R1/10 ,  G10K11/178 ,  H04R3/00 ,  H04R29/00

Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

公开(公告)号：US10148280B2

公开(公告)日：2018-12-04

申请号：US15853779

申请日：2017-12-23

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/44 ,  H03M1/10 ,  H03M1/18

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US10133293B2

公开(公告)日：2018-11-20

申请号：US15852757

申请日：2017-12-22

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Wai Lee

IPC: G05F3/26 ,  G05F1/10 ,  G05F3/02

Abstract: A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.

公开(公告)号：US20180232000A1

公开(公告)日：2018-08-16

申请号：US15955620

申请日：2018-04-17

Applicant: AVNERA CORPORATION

Inventor： Christopher D. Nilson

IPC: G05F3/16 ,  H03K17/687

CPC classification number: G05F3/16 ,  G05F1/468 ,  H03K17/687

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

公开(公告)号：US20180198430A1

公开(公告)日：2018-07-12

申请号：US15858101

申请日：2017-12-29

Applicant: Avnera Corporation

Inventor： Garry N. Link ,  Eric King ,  Xudong Zhao ,  Wai Lee ,  Alexander C. Stange ,  Amit Kumar

IPC: H03G3/00 ,  H03G3/32

CPC classification number: H03G3/004 ,  H03F1/025 ,  H03F1/305 ,  H03F3/187 ,  H03F2200/507 ,  H03F2200/511 ,  H03G3/32

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

公开(公告)号：US20180183455A1

公开(公告)日：2018-06-28

申请号：US15849220

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link ,  Jian Li

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/462 ,  H03M1/0863 ,  H03M1/1019 ,  H03M1/1061 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/129 ,  H03M1/466 ,  H03M1/468

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a successive approximation register (SAR) unit including one or more capacitive networks. The capacitive networks take a sample of an analog signal. The SAR also includes a comparator to approximate digital values based on the analog signal sample via successive comparison. The ADC includes a preamplifier coupled to the SAR unit. The preamplifier amplifies the analog signal for application to the capacitive networks for sampling. The ADC also includes a rough buffer coupled to the SAR unit. The rough buffer pre-charges the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier.

公开(公告)号：US09998819B2

公开(公告)日：2018-06-12

申请号：US15662698

申请日：2017-07-28

Applicant: Avnera Corporation

Inventor： Manpreet Singh Khaira ,  Thomas Irrgang

IPC: H04R1/20 ,  H04R1/28 ,  G06F1/16 ,  H04R1/02

CPC classification number: H04R1/20 ,  G06F1/1628 ,  G06F1/1632 ,  G06F2200/1633 ,  G06F2200/1634 ,  H04R1/026 ,  H04R1/28 ,  H04R1/2803 ,  H04R2205/021 ,  H04R2225/33 ,  H04R2400/03 ,  H04R2420/07

Abstract: A case having a recessed holding, an acoustic waveguide, and at least one audio transducer device. The recessed holding well is configured to receive and captively hold a stand-alone keyboard within the recessed holding well. The acoustic waveguide is integrated with a bottom cover of the case and between a bottom surface of the case and the recessed holding well. The at least one audio transducer device is coupled to a signal processing device and the acoustic waveguide. The at least one audio transducer device is configured to generate an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide is configured to receive the audible audio output and generate an enhanced bass audio output.