公开(公告)号：US08393778B2

公开(公告)日：2013-03-12

申请号：US13325345

申请日：2011-12-14

Applicant: Chi-Chen Cheng ,  Chi-Chung Lo

Inventor： Chi-Chen Cheng ,  Chi-Chung Lo

IPC: F21V7/04

CPC classification number: G02B6/0083 ,  G02F1/133615

Abstract: A backlight module and a wire positioning/holding device for the frame structure thereof are disclosed. The backlight module mainly includes a frame and a light source module. The light source module is disposed on the lateral side or on the bottom of the frame. The wire holding device mainly includes a main body and a winding pillar. A first guide slot is disposed on the main body, and the first guide slot has an inlet end and an outlet end. The winding pillar extends from the main body and is situated at one side of the first guide slot. The winding pillar and the main body together form a wire holding portion. The wire holding portion is disposed corresponding to the outlet end of the first guide slot to receive the wires of the light source module coming out of the outlet end.

Abstract translation: 公开了一种用于其框架结构的背光模块和线定位/保持装置。 背光模块主要包括框架和光源模块。 光源模块设置在框架的侧面或底部。 电线保持装置主要包括主体和卷绕支柱。 第一引导槽设置在主体上，第一引导槽具有入口端和出口端。 卷绕柱从主体延伸并位于第一导槽的一侧。 绕线柱和主体一起形成电线保持部分。 电线保持部分对应于第一引导槽的出口端设置，以接收从出口端出来的光源模块的电线。

公开(公告)号：US20130010560A1

公开(公告)日：2013-01-10

申请号：US13535075

申请日：2012-06-27

Applicant: Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

Inventor： Chung-Ji LU ,  Hung-Jen LIAO ,  Cheng Hung LEE ,  Derek C. TAO ,  Annie-Li-Keow LUM ,  Hong-Chen CHENG

IPC: H03F3/45 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C7/065

Abstract: A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.

Abstract translation: 电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。 第一电流镜电路具有参考端和镜像端。 第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。 第二个当前次级电路具有参考端和镜像端。 第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

公开(公告)号：US08280396B2

公开(公告)日：2012-10-02

申请号：US12007516

申请日：2008-01-11

Applicant: Rainer W. Bachl ,  Fang-Chen Cheng ,  Jung Ah Lee

Inventor： Rainer W. Bachl ,  Fang-Chen Cheng ,  Jung Ah Lee

IPC: H04W72/00

CPC classification number: H04W72/082 ,  H04W72/0426 ,  H04W92/20

Abstract: A method may include determining a metric for at least one physical resource block of a wireless cellular network in at least a one cell. Each physical resource block may include a set of frequencies, and/or the metric may be based on interference on the at least one physical resource block in the at least one cell. A determination of whether the metric violates a metric threshold may be made, and an overload indicator may be sent to at least one other cell if the metric violates the metric threshold.

Abstract translation: 一种方法可以包括确定至少一个小区中的无线蜂窝网络的至少一个物理资源块的度量。 每个物理资源块可以包括一组频率，和/或度量可以基于至少一个小区中的至少一个物理资源块上的干扰。 可以做出该度量是否违反度量阈值的确定，并且如果度量违反度量阈值，则可以向至少一个其他小区发送过载指示符。

公开(公告)号：US08279684B2

公开(公告)日：2012-10-02

申请号：US12842189

申请日：2010-07-23

Applicant: Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

Inventor： Hsu-Shun Chen ,  Cheng Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract translation: 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US08276192B2

公开(公告)日：2012-09-25

申请号：US12130243

申请日：2008-05-30

Applicant: Kay Schwendimann Anderson ,  Pau-Chen Cheng ,  Genady Ya. Grabarnik ,  Paul Ashley Karger ,  Marc Lelarge ,  Zhen Liu ,  Anton Viktorovich Riabov ,  Pankaj Rohatgi ,  Angela Marie Schuett ,  Grant Wagner

Inventor： Kay Schwendimann Anderson ,  Pau-Chen Cheng ,  Genady Ya. Grabarnik ,  Paul Ashley Karger ,  Marc Lelarge ,  Zhen Liu ,  Anton Viktorovich Riabov ,  Pankaj Rohatgi ,  Angela Marie Schuett ,  Grant Wagner

IPC: H04L29/06

CPC classification number: H04L63/10 ,  H04L63/20

Abstract: A method for security planning with hard security constraints includes: receiving security-related requirements of a network to be developed using system inputs and processing components; and generating the network according to the security-related requirements, wherein the network satisfies hard security constraints.

Abstract translation: 具有硬安全约束的安全规划方法包括：使用系统输入和处理组件接收要开发的网络的安全相关需求; 并根据安全性要求生成网络，其中网络满足严格的安全约束。

公开(公告)号：USD665763S1

公开(公告)日：2012-08-21

申请号：US29397417

申请日：2011-07-15

Applicant: Cheng-Chieh Tsai ,  Tzu-Cheng Yu ,  Hong-Xiu Luo ,  Ying-Chen Cheng

Designer： Cheng-Chieh Tsai ,  Tzu-Cheng Yu ,  Hong-Xiu Luo ,  Ying-Chen Cheng

公开(公告)号：US20120195139A1

公开(公告)日：2012-08-02

申请号：US13443619

申请日：2012-04-10

Applicant: Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

Inventor： Hsu-Shun CHEN ,  Cheng Hung LEE ,  Chung-Ji LU ,  Hong-Chen CHENG ,  Chung-Yi WU ,  Chih-Chieh CHIU

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/1048 ,  G11C5/14

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract translation: 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

公开(公告)号：US08227924B2

公开(公告)日：2012-07-24

申请号：US12835458

申请日：2010-07-13

Applicant: Cheng Hung Shen ,  Tin-Hao Kuo ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Yao-Chun Chuang

Inventor： Cheng Hung Shen ,  Tin-Hao Kuo ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Yao-Chun Chuang

IPC: H01L23/48

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11444 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14515 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/01007 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Abstract translation: 提供了与半导体器件一起使用的衬底对位。 活动柱和虚拟柱形成在第一基板上，使得虚拟柱可具有高于活动柱的高度的高度。 当将第一衬底连接到第二衬底时，虚拟柱作为支座，从而产生更大的均匀性。 在一个实施例中，虚拟柱可以通过形成具有用于虚拟柱的较小宽度的开口的图案化掩模而不是活性柱而同时形成为活性柱。 当使用电镀方法形成虚拟和活动柱时，图案化掩模中的虚拟柱形开口的较小宽度使虚拟柱具有比活动柱更大的高度。

公开(公告)号：US20120182792A1

公开(公告)日：2012-07-19

申请号：US13008992

申请日：2011-01-19

Applicant: Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

Inventor： Hong-Chen CHENG ,  Chih-Chieh CHIU ,  Hsu-Shun CHEN ,  Chung-Ji LU ,  Cheng-Hung LEE ,  Hung-Jen LIAO

IPC: G11C11/413 ,  G11C5/14

CPC classification number: G11C11/413

Abstract: A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.

Abstract translation: SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

公开(公告)号：US08207567B2

公开(公告)日：2012-06-26

申请号：US12274255

申请日：2008-11-19

Applicant: Chao-Chi Chin ,  Ming-Chu King ,  Chen Cheng Chou

Inventor： Chao-Chi Chin ,  Ming-Chu King ,  Chen Cheng Chou

IPC: H01L29/92

CPC classification number: H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

Abstract translation: 一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。