公开(公告)号：US07256569B2

公开(公告)日：2007-08-14

申请号：US11242915

申请日：2005-10-05

Applicant: Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

Inventor： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

IPC: G05F1/10 ,  G05F1/40 ,  H02H7/00

CPC classification number: G05F1/70

Abstract: The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

公开(公告)号：US20060109039A1

公开(公告)日：2006-05-25

申请号：US11282585

申请日：2005-11-21

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H03K3/017

CPC classification number: H02M3/33507 ,  H02M2001/0032 ,  H03K3/00 ,  H03K17/00 ,  H03K17/0822 ,  Y02B70/16

Abstract: A pulse width modulation device with a power saving mode controlled by an output voltage feedback hysteresis circuit is used in a power supply. The present invention comprises a hysteresis comparison circuit extracting a feedback voltage, a high threshold voltage and a low threshold voltage, and the voltages are executed by a comparison and hysteresis operation to a output blanking signal, a PWM control unit extracting a detecting current signal and the feedback voltage to output a modulation signal after a comparison operation is executed; an OR gate circuit connected to the hysteresis comparison circuit and the PWM control unit for receiving the blanking signal and the modulation signal to output a reset signal; and a synchronization signal output unit connected to the OR gate circuit for receiving the reset signal and an oscillation signal to output the drive signal.

Abstract translation: 在电源中使用具有由输出电压反馈滞后电路控制的省电模式的脉宽调制装置。 本发明包括提取反馈电压，高阈值电压和低阈值电压的滞后比较电路，并且通过对输出消隐信号进行比较和滞后操作来执行电压，PWM控制单元提取检测电流信号，以及 在执行比较操作之后输出调制信号的反馈电压; 连接到迟滞比较电路的OR门电路和用于接收消隐信号和调制信号以输出复位信号的PWM控制单元; 以及连接到或门电路的同步信号输出单元，用于接收复位信号和振荡信号以输出驱动信号。

公开(公告)号：US06406953B1

公开(公告)日：2002-06-18

申请号：US09053557

申请日：1998-04-01

Applicant: Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

Inventor： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC: H01L218238

CPC classification number: H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

Abstract translation: 动态随机存取存储器（DRAM）单元形成在偏置深N阱（DNW）中形成的P阱中。 在N个阱中形成PMOS晶体管。 NMOS通道停止注入掩模被修改为不是N阱掩模的反向，以阻止通道从用于DNW偏置的N +接触区域停止注入。 在DRAMS和其他集成电路中，通过布置相邻电路来消除一方面集成电路的阱与相邻电路之间的最小间隔要求，使得阱位于与具有电极的晶体管相邻的位置 连接到与电压偏压相同的电压。 例如，在DRAM中，通过将存储器访问之前的位线预先充电的晶体管旁边的DNW定位在DNW和读/写电路之间的最小间隔要求被消除。 晶体管的一个电极连接到预充电电压。 该电极与被偏置到相同预充电电压的DNW重叠。 该电极提供DNW N +接触区域。

公开(公告)号：US06284579B1

公开(公告)日：2001-09-04

申请号：US09418034

申请日：1999-10-14

Applicant: Jyh-Haur Wang ,  Bi-Ling Lin ,  Chung-Cheng Wu ,  Carlos H. Diaz

Inventor： Jyh-Haur Wang ,  Bi-Ling Lin ,  Chung-Cheng Wu ,  Carlos H. Diaz

IPC: H01L21338

CPC classification number: H01L29/66492 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/7833

Abstract: A method for forming within a substrate employed within a microelectronics fabrication a field effect transistor with attenuated drain leakage current. There is provided a silicon substrate within which are fabricated nMOS field effect transistors (FET) with lightly-doped n-type drain regions (nLDD) employing arsenic (As) dopant. There is then implanted indium (In) dopant atoms adjacent to the As diffused junction to form a p-type pocket therein. There is then avoided the customary high temperature rapid thermal annealing (RTA) step and instead employed a thermal annealing for 2 hours at 750 degrees centigrade, whereupon the implanted indium atom undergo transient enhanced diffusion (TED) to form a graded junction profile, resulting in attenuated drain leakage current and no increased reverse short channel effect from the strong segregation of indium into silicon oxide.

Abstract translation: 一种在微电子制造中采用的衬底内形成具有衰减漏极漏电流的场效应晶体管的方法。 提供了硅衬底，其中制造了使用砷（As）掺杂剂的具有轻掺杂n型漏极区（nLDD）的nMOS场效应晶体管（FET）。 然后将与In扩散结相邻的铟（In）掺杂剂原子注入到其中以形成p型凹穴。 然后避免了常规的高温快速热退火（RTA）步骤，并且替代地在750℃下进行2小时的热退火，随后注入的铟原子经历瞬时增强扩散（TED）以形成渐变连接轮廓，导致 衰减的漏极漏电流，并没有增加反向短沟道效应，从铟的强烈偏析到氧化硅。

公开(公告)号：US06248673B1

公开(公告)日：2001-06-19

申请号：US09511334

申请日：2000-02-23

Applicant: Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

Inventor： Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

IPC: H01L21469

CPC classification number: H01L29/518 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31629 ,  H01L21/324 ,  Y10S438/958

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device. The method is a “pure H2 (100%)” alloy recipe to use after contact opening or metal-1 formation.

Abstract translation: 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成微电子器件。 然后在微电子器件上形成由钝化介电材料形成的钝化介电层，该钝化介电材料选自氟硅酸盐玻璃（FSG）钝化介电材料，大气压化学气相沉积（APCVD）钝化介电材料，低于大气压的化学气相沉积 （SACVD）钝化介电材料和旋涂玻璃（SOG）钝化介电材料以从微电子器件形成钝化的微电子器件。 最后，在使用采用包含氢的气氛的热退火方法的同时进行退火，该钝化微电子器件形成稳定的钝化微电子器件。 该方法是在接触开口或金属-1形成之后使用的“纯H 2（100％）”合金配方。

公开(公告)号：US6144059A

公开(公告)日：2000-11-07

申请号：US375638

申请日：1999-08-17

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L27/108

CPC classification number: H01L28/84

Abstract: The present invention provides a process and a structure for increasing a capacitance of a stack capacitor. The process includes steps of: a) forming a contact hole on a silicon substrate having an oxide layer, b) forming a polysilicon contact plug of a first polysilicon layer in the contact hole; c) forming a second gibbous polysilicon layer on a surface of the contact plug, and d) forming a third polysilicon layer above the gibbous polysilicon layer and a portion of the oxide layer to form the stack capacitor, wherein the gibbous polysilicon layer increases the capacitance of the stack capacitor.

公开(公告)号：US6063548A

公开(公告)日：2000-05-16

申请号：US148565

申请日：1998-09-04

Applicant: Wen-Ting Chu ,  Chung-Cheng Wu

Inventor： Wen-Ting Chu ,  Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242 ,  G03C5/00

CPC classification number: H01L28/92 ,  H01L27/10852

Abstract: A method for forming stacked capacitors for DRAMs using a single photoresist mask and having bottom electrodes self-aligned to node contacts is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. A first silicon nitride (Si.sub.3 N.sub.4) hard mask layer is deposited and a second insulating layer is deposited. First openings are etched, partially into the first insulating layer, for the capacitor bottom electrodes. A second Si.sub.3 N.sub.4 layer is deposited and etched back to form sidewall spacers in the first openings. The Si.sub.3 N.sub.4 hard mask and spacers are used to etch second openings (node contacts) in the first insulating layer, self-aligned in the first openings and to the source/drain contact areas. A first polysilicon layer is deposited and etched back to form recessed polysilicon plugs in the first openings. A third Si.sub.3 N.sub.4 layer is deposited and etched back to form sidewall spacers on the plugs in the first openings and is used as a mask to etch the polysilicon to form the vertical sidewalls of the bottom electrodes self-aligned to the node contacts. The first insulating layer is recessed to expose the bottom electrodes. An interelectrode dielectric layer is formed on the bottom electrodes, and a patterned second polysilicon layer is used for the top electrodes.

Abstract translation: 实现了使用单个光致抗蚀剂掩模形成用于DRAM的堆叠电容器并且具有与节点接触自对准的底部电极的方法。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。 沉积第一氮化硅（Si 3 N 4）硬掩模层并沉积第二绝缘层。 对于电容器底部电极，第一开口部分地被蚀刻到第一绝缘层中。 第二Si 3 N 4层被沉积并回蚀刻以在第一开口中形成侧壁间隔物。 Si 3 N 4硬掩模和间隔物用于蚀刻第一绝缘层中的第二开口（节点接触），在第一开口中和源/漏接触区域中自对准。 沉积第一多晶硅层并将其回蚀刻以在第一开口中形成凹陷的多晶硅塞。 沉积第三个Si 3 N 4层并回蚀刻以在第一开口中的插塞上形成侧壁间隔物，并且用作掩模以蚀刻多晶硅以形成与节点接触件自对准的底部电极的垂直侧壁。 第一绝缘层凹进露出底部电极。 在底部电极上形成电极间电介质层，并且将图案化的第二多晶硅层用于顶部电极。

公开(公告)号：US5436190A

公开(公告)日：1995-07-25

申请号：US344007

申请日：1994-11-23

Applicant: Ming-Tzong Yang ,  Chung-Cheng Wu

Inventor： Ming-Tzong Yang ,  Chung-Cheng Wu

IPC: H01L21/763 ,  H01L21/76

CPC classification number: H01L21/763

Abstract: A method for fabricating a very narrow electrical isolation trench in a semiconductor substrate for isolating the individual field effect transistors (FETs) is achieved. This method eliminates the oxide encroachment into the device area associated with LOCOS techniques, thereby increasing device density. The method involves etching trenches, less than one half micrometer in width in the silicon substrate and forming sidewall spacer in the trench. The trench is filled with doped polysilicon and planarized, forming a trench which is planar with the device region. These isolation trenches are made in both N and P-wells for fabricating CMOS circuits having ULSI densities.

Abstract translation: 实现了用于在用于隔离各个场效应晶体管（FET）的半导体衬底中制造非常窄的电隔离沟槽的方法。 该方法消除了与LOCOS技术相关的器件区域的氧化物侵蚀，从而增加器件密度。 该方法包括蚀刻在硅衬底中宽度小于半微米的沟槽，并在沟槽中形成侧壁间隔物。 沟槽填充有掺杂的多晶硅并且被平坦化，形成与器件区域平坦的沟槽。 这些隔离沟槽在N阱和P阱中制造，用于制造具有ULSI密度的CMOS电路。

公开(公告)号：US08759943B2

公开(公告)日：2014-06-24

申请号：US12900626

申请日：2010-10-08

Applicant: Chih-Hung Tseng ,  Da-Wen Lin ,  Chien-Tai Chan ,  Chia-Pin Lin ,  Li-Wen Weng ,  An-Shen Chang ,  Chung-Cheng Wu

Inventor： Chih-Hung Tseng ,  Da-Wen Lin ,  Chien-Tai Chan ,  Chia-Pin Lin ,  Li-Wen Weng ,  An-Shen Chang ,  Chung-Cheng Wu

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7853

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract translation: 晶体管包括覆盖在浅沟槽隔离层下面的切口鳍。 可以使用一个或多个凹口，其尺寸可以沿翅片的横向方向变化。 在一些实施例中，使用根据硅取向选择性的各向异性湿蚀刻形成凹口。 实例湿蚀刻剂是氢氧化四甲基铵（TMAH）或氢氧化钾（KOH）。

公开(公告)号：US08362573B2

公开(公告)日：2013-01-29

申请号：US12787966

申请日：2010-05-26

Applicant: Chung-Cheng Wu ,  Ali Keshavarzi ,  Ka Hing Fung ,  Ta-Pen Guo ,  Jiann-Tyng Tzeng ,  Yen-Ming Chen ,  Shyue-Shyh Lin ,  Shyh-Wei Wang ,  Sheng-Jier Yang ,  Hsiang-Jen Tseng ,  David B. Scott ,  Min Cao

Inventor： Chung-Cheng Wu ,  Ali Keshavarzi ,  Ka Hing Fung ,  Ta-Pen Guo ,  Jiann-Tyng Tzeng ,  Yen-Ming Chen ,  Shyue-Shyh Lin ,  Shyh-Wei Wang ,  Sheng-Jier Yang ,  Hsiang-Jen Tseng ,  David B. Scott ,  Min Cao

IPC: H01L29/76

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/7848 ,  H01L2224/16225

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.

Abstract translation: 集成电路包括用于第一类型晶体管的第一扩散区域。 第一类型晶体管包括第一漏极区域和第一源极区域。 用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。 第二类型晶体管包括第二漏极区域和第二源极区域。 栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。 第一金属层与第一源区电耦合。 第一金属层和第一扩散区域与第一距离重叠。 第二金属层与第一漏极区域和第二漏极区域电耦合。 第二金属层和第一扩散区域与第二距离重叠。 第一距离大于第二距离。