公开(公告)号：US20180308007A1

公开(公告)日：2018-10-25

申请号：US15766755

申请日：2016-10-14

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mohammad H.S. Amin ,  Evgeny Andriyash ,  Jason Rolfe

IPC: G06N99/00

CPC classification number: G06N99/005 ,  B82Y10/00 ,  G06N3/0445 ,  G06N99/002

Abstract: A hybrid computer generates samples for machine learning. The hybrid computer includes a processor that implements a Boltzmann machine, e.g., a quantum Boltzmann machine, which returns equilibrium samples from eigenstates of a quantum Hamiltonian. Subsets of samples are provided to training and validations modules. Operation can include: receiving a training set; preparing a model described by an Ising Hamiltonian; initializing model parameters; segmenting the training set into subsets; creating a sample set by repeatedly drawing samples until the determined number of samples has been drawn; and updating the model. Operation can include partitioning the training set into input and output data sets, and determining a conditional probability distribution that describes a probability of observing an output vector given a selected input vector, e.g., determining a conditional probability by performing a number of operations to minimize an upper bound for a log-likelihood of the conditional probability distribution.

公开(公告)号：US20180240034A1

公开(公告)日：2018-08-23

申请号：US15752102

申请日：2016-08-11

Applicant: D-Wave Systems Inc.

Inventor： Richard G. Harris

IPC: G06N99/00 ,  H01F38/14 ,  B82Y10/00 ,  H01L27/18 ,  H03K19/195

CPC classification number: G06N10/00 ,  B82Y10/00 ,  H01F38/14 ,  H01F2038/143 ,  H01L27/18 ,  H03K19/195

Abstract: A higher degree of interactions between qubits is realizable. This disclosure generally relates to devices, and architectures for quantum instruments comprising quantum devices and techniques for operating the same. Systems and processors for creating and using higher degree interactions between qubits may be found herein. Higher order interactions include interactions among three or more qubits. Methods for creating and using higher degree interactions among three or more qubits on a quantum processor may be found herein.

公开(公告)号：US20180150728A1

公开(公告)日：2018-05-31

申请号：US15822884

申请日：2017-11-27

Applicant: D-Wave Systems Inc.

Inventor： Arash Vahdat

IPC: G06K9/62 ,  G06N5/04 ,  G06N3/04

CPC classification number: G06K9/6278 ,  G06K9/6232 ,  G06K9/6256 ,  G06N3/0427 ,  G06N3/0454 ,  G06N3/0472 ,  G06N3/08 ,  G06N5/04 ,  G06N7/005

Abstract: Machine learning classification models which are robust against label noise are provided. Noise may be modelled explicitly by modelling “label flips”, where incorrect binary labels are “flipped” relative to their ground truth value. Distributions of label flips may be modelled as prior and posterior distributions in a flexible architecture for machine learning systems. An arbitrary classification model may be provided within the system. The classification model is made more robust to label noise by operation of the prior and posterior distributions. Particular prior and approximating posterior distributions are disclosed.

公开(公告)号：US09881256B2

公开(公告)日：2018-01-30

申请号：US15505522

申请日：2015-08-21

Applicant: D-Wave Systems Inc.

Inventor： Firas Hamze ,  Andrew Douglas King ,  Jack Raymond ,  Aidan Patrick Roy ,  Robert Israel ,  Evgeny Andriyash ,  Catherine McGeoch ,  Mani Ranjbar

IPC: H03K19/195 ,  G06N99/00 ,  G06N3/12 ,  G06F9/02 ,  G06F15/18 ,  G06F15/76 ,  G06F9/32 ,  G06F17/10

CPC classification number: G06N99/002 ,  G06F9/02 ,  G06F9/32 ,  G06F15/18 ,  G06F15/76 ,  G06F17/10 ,  G06N3/12

Abstract: Computational systems implement problem solving using heuristic solvers or optimizers. Such may iteratively evaluate a result of processing, and modify the problem or representation thereof before repeating processing on the modified problem, until a termination condition is reached. Heuristic solvers or optimizers may execute on one or more digital processors and/or one or more quantum processors. The system may autonomously select between types of hardware devices and/or types of heuristic optimization algorithms. Such may coordinate or at least partially overlap post-processing operations with processing operations, for instance performing post-processing on an ith batch of samples while generating an (i+1)th batch of samples, e.g., so post-processing operation on the ith batch of samples does not extend in time beyond the generation of the (i+1)th batch of samples. Heuristic optimizers selection is based on pre-processing assessment of the problem, e.g., based on features extracted from the problem and for instance, on predicted success.

公开(公告)号：US09865648B2

公开(公告)日：2018-01-09

申请号：US14109604

申请日：2013-12-17

Applicant: D-Wave Systems Inc.

Inventor： Paul I. Bunyk

IPC: H01L27/18 ,  H01L39/04 ,  H01L23/00 ,  H01L39/24 ,  G01R31/28

CPC classification number: H01L27/18 ,  G01R31/2884 ,  G01R31/2891 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L39/045 ,  H01L39/24 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05179 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13163 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/15787 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01076 ,  H01L2224/81 ,  H01L2924/00

Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

公开(公告)号：US09699266B2

公开(公告)日：2017-07-04

申请号：US14162557

申请日：2014-01-23

Applicant: D-Wave Systems Inc.

Inventor： Geordie Rose ,  Paul I. Bunyk

IPC: G06F15/76 ,  G06F17/50 ,  H04L29/08 ,  G06F15/78 ,  G06N99/00 ,  H04B10/70 ,  H04L12/725 ,  H04Q11/00

CPC classification number: H04L67/34 ,  G06F15/7825 ,  G06N99/002 ,  H04B10/70 ,  H04L45/306 ,  H04L67/327 ,  H04Q11/0066 ,  H04Q2011/0073

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

公开(公告)号：US20170178017A1

公开(公告)日：2017-06-22

申请号：US15338915

申请日：2016-10-31

Applicant: D-Wave Systems Inc.

Inventor： Aidan Patrick Roy ,  William G. Macready

IPC: G06N99/00 ,  G06N5/00

CPC classification number: G06N10/00 ,  B82Y10/00 ,  G06N5/003 ,  G06N20/00

Abstract: Systems and methods allow formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor). In a first stage, sets of connected subgraphs are successively generated, each set including a respective subgraph for each decision variable in the problem graph, adjacent decisions variables in the problem graph mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph. In a second stage, the connected subgraphs are refined such that no vertex represents more than a single decision variable.

公开(公告)号：US20170177751A1

公开(公告)日：2017-06-22

申请号：US15419083

申请日：2017-01-30

Applicant: D-Wave Systems Inc.

Inventor： William G. Macready ,  Geordie Rose ,  Thomas F.W. Mahon ,  Peter Love ,  Marshall Drew-Brook

IPC: G06F17/50 ,  G06N99/00 ,  G06F17/11

CPC classification number: G06F17/505 ,  B82Y10/00 ,  G06F17/11 ,  G06N99/002

Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.

公开(公告)号：US09634224B2

公开(公告)日：2017-04-25

申请号：US14600962

申请日：2015-01-20

Applicant: D-Wave Systems Inc.

Inventor： Eric Ladizinsky ,  Nicolas Ladizinsky ,  Jason Yao ,  Byong Hyop Oh ,  Richard David Neufeld

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/22

CPC classification number: H01L39/2493 ,  H01L27/18 ,  H01L39/223

Abstract: In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion.

公开(公告)号：US20170091650A1

公开(公告)日：2017-03-30

申请号：US15373910

申请日：2016-12-09

Applicant: D-Wave Systems Inc.

Inventor： Andrew Douglas King

IPC: G06N99/00 ,  G06F15/76

CPC classification number: G06N99/002 ,  G06F15/76 ,  H03K19/195

Abstract: Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Angular deviations between qubits in one set may allow qubits in the same set to cross one another. Each unit cell is positioned proximally adjacent at least one other unit cell. Communicatively coupling between qubits is realized through respective intra-cell and inter-cell coupling devices.