公开(公告)号：US08553445B2

公开(公告)日：2013-10-08

申请号：US13224410

申请日：2011-09-02

申请人： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

发明人： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

IPC分类号： G11C11/00

CPC分类号： H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

摘要： Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

摘要翻译： 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US08547766B2

公开(公告)日：2013-10-01

申请号：US12659883

申请日：2010-03-24

申请人： Jong-Hak Won ,  Hyang-Ja Yang ,  Choong-Sun Shin ,  Hak-Soo Yu ,  Young-Soo An ,  Jung-Hyeon Kim

发明人： Jong-Hak Won ,  Hyang-Ja Yang ,  Choong-Sun Shin ,  Hak-Soo Yu ,  Young-Soo An ,  Jung-Hyeon Kim

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C11/4097

摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.

摘要翻译： 数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间 垫

公开(公告)号：US20130060985A1

公开(公告)日：2013-03-07

申请号：US13606551

申请日：2012-09-07

申请人： Hak-Soo Yu ,  Jun-Jin Kong ,  Hyoung-Joon Kim ,  Joo-Young Hwang ,  In-Su Choi

发明人： Hak-Soo Yu ,  Jun-Jin Kong ,  Hyoung-Joon Kim ,  Joo-Young Hwang ,  In-Su Choi

IPC分类号： G06F13/16

CPC分类号： G06F13/16 ,  G06F13/1694 ,  G06F13/385

摘要： A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit.

摘要翻译： 设备包括存储器控制器，耦合到存储器控制器的存储器总线，内部存储器和外部存储器连接单元。 内部存储器可以通过存储器总线直接连接到存储器控制器。 外部存储器连接单元可以通过存储器总线中的一部分信号线将外部存储器直接连接到存储器控制器，并且可以产生指示外部存储器是否连接到外部存储器连接单元的标志信号。

公开(公告)号：US20120230139A1

公开(公告)日：2012-09-13

申请号：US13413938

申请日：2012-03-07

申请人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

发明人： Jong-pil Son ,  Chul-woo Park ,  Young-hyun Jun ,  Hong-sun Hwang ,  Hak-soo Yu

IPC分类号： G11C7/06 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

摘要翻译： 一种半导体存储器件，包括连接到存储单元的位线和被配置为响应于位线的电压电平驱动全局位线的电压电平的读出放大器。 感测放大器提供与存储在存储器单元中的数据互补的数据到全局位线，并且在存储器单元的有效操作期间将全局位线的互补数据提供给存储单元。

公开(公告)号：US20120212989A1

公开(公告)日：2012-08-23

申请号：US13304851

申请日：2011-11-28

申请人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

发明人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

IPC分类号： G11C5/02

CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

公开(公告)号：US20120020142A1

公开(公告)日：2012-01-26

申请号：US13184795

申请日：2011-07-18

申请人： Hak Soo Yu ,  In Gyu Baek ,  Hong Sun Hwang ,  Su A. Kim ,  Mu Jin Seo

发明人： Hak Soo Yu ,  In Gyu Baek ,  Hong Sun Hwang ,  Su A. Kim ,  Mu Jin Seo

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71

摘要： Provided is a semiconductor resistive memory device. The resistive memory device includes a plurality of unit cells. A source line and a data input/output line of the unit cells may be selectively connected to have a substantially same voltage level for equalization when the unit cells are in inactive or unselected state. The equalization may decrease current consumption and protect write error, and protect leakage current.

摘要翻译： 提供了半导体电阻式存储器件。 电阻式存储器件包括多个单元电池。 单位单元的源极线和数据输入/输出线可以被选择性地连接以具有基本上相同的电压电平以用于在单位电池处于非活动状态或未选择状态时进行均衡。 均衡可能会降低电流消耗并保护写入错误，并保护漏电流。

公开(公告)号：US20110305100A1

公开(公告)日：2011-12-15

申请号：US13152316

申请日：2011-06-03

申请人： Hak-soo YU ,  In-gyu BAEK ,  Hong-sun Hwang ,  Young-kug MOON

发明人： Hak-soo YU ,  In-gyu BAEK ,  Hong-sun Hwang ,  Young-kug MOON

IPC分类号： G11C5/14

CPC分类号： G11C5/063 ,  G11C5/025

摘要： A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers

摘要翻译： 一种半导体存储器件，包括多个层，每个层包括存储单元阵列并彼此堆叠; 以及用于向层供电的至少一个电力平面。 电力平面包括施加电源电压的区域和施加接地电压的区域。 施加电源电压的区域位于与施加接地电压的区域相邻的位置处，并且在其间形成去耦电容器以将功率噪声流入到层中或在层中产生功率噪声

公开(公告)号：US07616512B2

公开(公告)日：2009-11-10

申请号：US12347233

申请日：2008-12-31

申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

IPC分类号： G11C7/00

CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

公开(公告)号：US20090154265A1

公开(公告)日：2009-06-18

申请号：US12347239

申请日：2008-12-31

申请人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

发明人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

IPC分类号： G11C11/416 ,  G11C8/00

CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

公开(公告)号：US5991233A

公开(公告)日：1999-11-23

申请号：US947090

申请日：1997-10-08

申请人： Hak-soo Yu

发明人： Hak-soo Yu

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1072

摘要： A switch signal generator simultaneously sets every input and output data path in a high-speed synchronous SRAM. The switch signal generator receives control signals and a plurality of input signals, generates a plurality of switch signals, and sequentially enables other switch signals when a first switch signal of the plurality of switch signals is enabled. The synchronous SRAM includes an output data path/data storing portion, an input data path/data storing portion, and a path switch controlling portion. All burst orders are set simultaneously in the path switch controlling portion including the switch signal generator when a burst operation starts, and all data paths of the output data path/data storing portion and the input data path/data storing portion are simultaneously set by switch control signals which are provided by the path switch controlling portion.

摘要翻译： 开关信号发生器同时设置高速同步SRAM中的每个输入和输出数据路径。 开关信号发生器接收控制信号和多个输入信号，产生多个开关信号，并且当多个开关信号的第一开关信号被使能时，顺序启动其它开关信号。 同步SRAM包括输出数据路径/数据存储部分，输入数据路径/数据存储部分和路径切换控制部分。 当突发操作开始时，包括开关信号发生器的路径切换控制部分同时设置所有突发命令，并且通过开关同时设置输出数据路径/数据存储部分和输入数据路径/数据存储部分的所有数据路径 由路径切换控制部提供的控制信号。