公开(公告)号：US20030087496A1

公开(公告)日：2003-05-08

申请号：US09992880

申请日：2001-11-05

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/336

CPC classification number: H01L27/0658 ,  H01L21/31144 ,  H01L21/76802 ,  H01L27/067 ,  H01L27/0811

Abstract: The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

Abstract translation: 本发明涉及具有MOS电容器的集成电路。 在一个实施例中，形成集成电路的方法包括在衬底的表面上形成氧化物层，所述衬底具有多个隔离岛。 每个隔离岛用于形成半导体器件。 对氧化物层进行构图以暴露衬底表面的预定区域。 沉积覆盖氧化物层的氮化物层和衬底的暴露的表面区域。 将离子注入氮化物层，其中氮化物层是用于注入离子的注入屏。 在形成电容器时使用氮化物层作为电容器电介质。 此外，进行干蚀刻以形成延伸穿过氮化物层并通过氧化物层的接触开口，以接触形成在衬底中的选定器件区域。

公开(公告)号：US20020185696A1

公开(公告)日：2002-12-12

申请号：US10104342

申请日：2002-03-22

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L029/76

CPC classification number: H01L29/66659 ,  H01L29/0634 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

Abstract translation: 具有改进的击穿电压的集成电路的高电压侧向半导体器件。 该半导体器件包括半导体本体，形成在半导体本体中的延伸漏极区，源极和漏极腔，形成与延伸漏极区的pn结的顶部栅极，半导体主体的表面上的绝缘层和形成的栅极 在绝缘层上。 此外，半导体材料的高掺杂阱形成在顶栅区内，其具有比顶栅区其余部分更高的集成掺杂。 这种较高掺杂的半导体材料袋在器件操作期间不会完全消耗。 此外，栅极通过场效应控制电流通过在源极袋和延伸的漏极区域的最近点之间横向形成的沟道。

公开(公告)号：US20020097545A1

公开(公告)日：2002-07-25

申请号：US09862990

申请日：2001-05-22

Applicant: Intersil Americas Inc.

Inventor： Grady M. Wood

IPC: H02H009/02

CPC classification number: H04M3/18 ,  H04M3/005 ,  H04M2201/06

Abstract: A switch includes first and second switch terminals, at least one output MOS transistor for selectively connecting the first and second switch terminals, and a driving current source for driving the at least one output MOS transistor. The switch may also include a current limiter for limiting the driving of the at least one output MOS transistor by the driving current source to establish a current limit. Furthermore, a controller may be included for the current limiter for controlling the current limit, such as by causing the current limiter to decrease the current limit based upon an increase in temperature of the integrated circuit or at periodic intervals to control rise and fall times of the at least one output MOS transistor.

Abstract translation: 开关包括第一和第二开关端子，用于选择性地连接第一和第二开关端子的至少一个输出MOS晶体管和用于驱动至少一个输出MOS晶体管的驱动电流源。 开关还可以包括限流器，用于限制由驱动电流源驱动至少一个输出MOS晶体管以建立电流限制。 此外，例如通过使限流器基于集成电路的温度升高或者以周期性间隔来降低电流限制，控制电流限制器的控制器用于控制电流限制，以控制电流限制器的上升和下降时间 所述至少一个输出MOS晶体管。

公开(公告)号：US20020095641A1

公开(公告)日：2002-07-18

申请号：US10021150

申请日：2001-10-30

Applicant: Intersil Americas Inc.

Inventor： Eric Noel Cartagena

IPC: G06F011/18

CPC classification number: H03K3/0375

Abstract: A redundant latch circuit resistant to SEUs includes a plurality of latches, a majority voting circuit having inputs connected to the latch outputs, and a feedback reset circuit connected to the latch outputs and driving the latch reset inputs. The majority voting circuit indicates a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise. The feedback reset circuit may have inputs connected to the outputs of the latches, and outputs connected to the reset inputs of the latches. The feedback reset circuit may switch at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state to thereby provide resistance to SEUs.

Abstract translation: 一个耐SEU的冗余锁存电路包括多个锁存器，多数投票电路具有连接到锁存器输出的输入端，反馈复位电路连接到锁存器输出端并驱动锁存复位输入端。 大多数投票电路基于大多数锁存器处于设置状态并指示复位状态，指示冗余锁存电路的设置状态。 反馈复位电路可以具有连接到锁存器的输出的输入，以及连接到锁存器的复位输入的输出。 当至少一个其他锁存器保持在复位状态时，反馈复位电路可以将至少一个锁存器从SEU引起的变化切换回到复位状态，从而提供对SEU的电阻。

公开(公告)号：US20020036583A1

公开(公告)日：2002-03-28

申请号：US09901327

申请日：2001-07-09

Applicant: INTERSIL AMERICAS INC.

Inventor： Leonel Ernesto Enriquez

IPC: H03M001/34

CPC classification number: H03F3/3066

Abstract: A non-sampling cascaded current mode analog-to-digital converter is formed of cascaded threshold detector bit cells driven by a transconductance amplifier for substantially instantaneously propagated current mode operation. A front end stage receives an input voltage representative of the quantity to be digitized, and outputs a pair of currents to Nnull1 cascaded, identically configured threshold comparator-based bit cells, N being the number of bits of resolution of the converter. A bit cell resolves a digital bit and couples a pair of output currents to the next bit cell. The Nnull1th bit cell in the cascaded architecture is configured to provide both the next to least significant bit and the least significant bit.

公开(公告)号：US09001911B2

公开(公告)日：2015-04-07

申请号：US13706290

申请日：2012-12-05

Applicant: Intersil Americas Inc.

Inventor： Mark Fimoff ,  Greg Tomezak

IPC: H04L23/02 ,  H04L27/34 ,  H04L5/00 ,  H04L27/26 ,  H04L1/00

CPC classification number: H04L27/36 ,  H04L1/0045 ,  H04L1/0054 ,  H04L1/0057 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/003 ,  H04L5/0046 ,  H04L5/16 ,  H04L27/2608 ,  H04L27/2647 ,  H04L27/2655 ,  H04L27/34

Abstract: A DMT system for a half-duplex two-way link carries Internet protocol encoded video stream on a coaxial cable that also carries a baseband rendition of the same video stream. A plurality of downlink symbols modulated on a subband of subcarriers in a downlink signal are decoded. The symbols may carry data encoded on a subband using a constellation of QAM symbols assigned to the subband. Other subbands may be associated with different QAM constellations. Lower-order constellations of QAM symbols may be assigned to subbands that include higher-frequency subcarriers and higher-order constellations of QAM symbols may be assigned to subbands that include lower-frequency subcarriers. A block error correction decoder may be synchronized based on an identification of the first constellation of QAM symbols and information identifying boundaries between the plurality of downlink symbols.

Abstract translation: 用于半双工双向链路的DMT系统在同轴电缆上承载互联网协议编码的视频流，该同轴电缆还携带相同视频流的基带再现。 解码在下行链路信号中的子载波的子带上调制的多个下行链路符号。 符号可以使用分配给子带的QAM符号的星座携带在子带上编码的数据。 其他子带可能与不同的QAM星座相关联。 可以将QAM符号的低阶星座分配给包括较高频率子载波的子带，并且可以将QAM符号的高阶星座分配给包括较低频率子载波的子带。 可以基于QAM符号的第一星座的标识和识别多个下行链路符号之间的边界的信息来同步块纠错解码器。

公开(公告)号：US20140113444A1

公开(公告)日：2014-04-24

申请号：US14145218

申请日：2013-12-31

Applicant: INTERSIL AMERICAS INC.

Inventor： John T. Gasner ,  Michael D. Church ,  Sameer D. Parab ,  Paul E. Bakeman, JR. ,  David A. Decrosta ,  Robert Lomenick ,  Chris A. McCarty

IPC: H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/32051 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/528 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

Abstract translation: 半导体结构包括顶部金属层，形成在顶部金属层上的接合焊盘，形成在顶部金属层下面的导体以及将导体与顶部金属层分开的绝缘层。 与顶部金属层的剩余部分相比，顶部金属层包括相对刚性材料的子层。 相对硬的材料的子层被配置为在绝缘层上分布应力以减少绝缘层中的开裂。

公开(公告)号：US20130285226A1

公开(公告)日：2013-10-31

申请号：US13932076

申请日：2013-07-01

Applicant: INTERSIL AMERICAS INC.

Inventor： Randolph Cruz

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49541 ,  H01L2224/32245

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

公开(公告)号：US20130148027A1

公开(公告)日：2013-06-13

申请号：US13760592

申请日：2013-02-06

Applicant: INTERSIL AMERICAS INC.

Inventor： David W. Ritter ,  Robert David Zucker ,  Warren Craddock

IPC: H04N5/21

CPC classification number: H04N5/21 ,  H04B3/145 ,  H04N7/102 ,  H04N7/108

Abstract: Provided herein are methods and systems that provide automatic compensation for frequency attenuation of a video signal transmitted over a cable. In accordance with an embodiment, a system includes an equalizer and a compensation controller. The equalizer receives a video signal that was transmitted over a cable, provides compensation for frequency attenuation that occurred during the transmission over the cable, and outputs a compensated video signal. The compensation controller automatically adjusts the compensation provided by the equalizer based on comparisons of one or more portions of the compensated video signal to one or more reference voltage levels.

Abstract translation: 本文提供了对通过电缆传输的视频信号的频率衰减提供自动补偿的方法和系统。 根据实施例，系统包括均衡器和补偿控制器。 均衡器接收通过电缆传输的视频信号，提供在通过电缆传输期间发生的频率衰减的补偿，并输出经补偿的视频信号。 补偿控制器基于将补偿的视频信号的一个或多个部分与一个或多个参考电压电平进行比较，自动调整由均衡器提供的补偿。

公开(公告)号：US20040178940A1

公开(公告)日：2004-09-16

申请号：US10389374

申请日：2003-03-14

Applicant: Intersil Americas Inc.

Inventor： Harold Allen Wittlinger

IPC: H03M001/66 ,  H03M001/10

CPC classification number: H03M1/002 ,  H03M1/66

Abstract: A voltage margin setting interface circuit has a single input pin, and is configured to program the slew rate and polarity direction of variation of the operation of a digital-to-analog converter, such as may be used to set a reference voltage level, for application to an error amplifier of a voltage regulator circuit of the power supply of a personal computer. A DAC clocking control circuit is coupled to an output port, and to respective DAC increment and decrement ports, and is operative to control the magnitude of output current, and to assert an output signal at one of the increment and decrement ports, in accordance with a prescribed relationship between the voltage and upper and lower ranges of the input voltage relative to its middle value.

Abstract translation: 电压余量设定接口电路具有单个输入引脚，并且被配置为对数/模转换器的操作变化的转换速率和极性方向进行编程，诸如可用于设置参考电压电平，以供 应用于个人计算机的电源的电压调节器电路的误差放大器。 DAC时钟控制电路耦合到输出端口和相应的DAC增量和减小端口，并且可操作以控制输出电流的大小，并且根据增量和减量端口中的一个端口断言输出信号 电压与输入电压的上下范围相对于其中间值的规定关系。