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    Methods of forming silicide strapping in imager transfer gate device
    44.
    发明授权
    Methods of forming silicide strapping in imager transfer gate device 有权
    在成像器传输门装置中形成硅化物带的方法

    公开(公告)号：US08158453B2

    公开(公告)日：2012-04-17

    申请号：US12699419

    申请日：2010-02-03

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC: H01L21/336

    CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

    CMOS image sensor with reduced dark current
    47.
    发明授权
    CMOS image sensor with reduced dark current 有权
    具有降低暗电流的CMOS图像传感器

    公开(公告)号：US08105861B2

    公开(公告)日：2012-01-31

    申请号：US12885648

    申请日：2010-09-20

    Applicant: James W. Adkisson ,  Rajendran Krishnasamy

    Inventor： James W. Adkisson ,  Rajendran Krishnasamy

    IPC: H01L21/00

    CPC classification number: H01L27/14603

    Abstract: A carbon-containing semiconductor layer is formed on exposed surfaces of a p− doped semiconductor layer abutting sidewalls of a shallow trench. Following formation of a dielectric layer on the carbon-containing semiconductor layer, a surface pinning layer having a p-type doping is formed underneath the carbon-containing semiconductor layer. A shallow trench isolation structure and a photodiode are subsequently formed. Diffusion of defects directly beneath the shallow trench isolation structure, now contained in the carbon-containing semiconductor layer, is suppressed. Further, boron diffusion into the shallow trench isolation structure and into the photodiode is also suppressed by the carbon-containing semiconductor layer, providing reduction in dark current and enhancement of performance of the photodiode.

    Abstract translation: 在邻接浅沟槽的侧壁的p掺杂半导体层的暴露表面上形成含碳半导体层。 在含碳半导体层上形成电介质层之后，在含碳半导体层的下面形成具有p型掺杂的表面钉扎层。 随后形成浅沟槽隔离结构和光电二极管。 现在包含在含碳半导体层中的浅沟槽隔离结构正下方的缺陷的扩散被抑制。 此外，通过含碳半导体层也抑制了进入浅沟槽隔离结构并进入光电二极管的硼，从而提供了暗电流的降低和光电二极管的性能的提高。

    Isolation with offset deep well implants
    48.
    发明授权
    Isolation with offset deep well implants 有权
    隔离与偏移深井植入物

    公开(公告)号：US08034699B2

    公开(公告)日：2011-10-11

    申请号：US12464206

    申请日：2009-05-12

    Applicant: James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  Mark D. Jaffe ,  Alain Loiseau

    IPC: H01L21/425

    CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/823892

    Abstract: A method implants impurities into well regions of transistors. The method prepares a first mask over a substrate and performs a first shallow well implant through the first mask to implant first-type impurities to a first depth of the substrate. The first mask is removed and a second mask is prepared over the substrate. The method performs a second shallow well implant through the second mask to implant second-type impurities to the first depth of the substrate and then removes the second mask. A third mask is prepared over the substrate. The third mask has openings smaller than openings in the first mask and the second mask. A first deep well implant is performed through the third mask to implant the first-type impurities to a second depth of the substrate, the second depth of the substrate being greater than the first depth of the substrate. The third mask is removed and a fourth mask is prepared over the substrate, the fourth mask has openings smaller than the openings in the first mask and the second mask. Then, a second deep well implant is performed through the fourth mask to implant the second-type impurities to the second depth of the substrate.

    Abstract translation: 一种方法是将杂质掺入晶体管的阱区。 该方法在衬底上制备第一掩模，并且通过第一掩模执行第一浅阱注入，以将第一类型杂质注入到衬底的第一深度。 去除第一个掩模，并在衬底上制备第二个掩模。 该方法通过第二掩模执行第二浅井注入，以将第二类型杂质植入衬底的第一深度，然后移除第二掩模。 在衬底上制备第三个掩模。 第三掩模具有比第一掩模和第二掩模中的开口小的开口。 通过第三掩模执行第一深孔注入，以将第一类型的杂质注入衬底的第二深度，衬底的第二深度大于衬底的第一深度。 去除第三掩模并在衬底上制备第四掩模，第四掩模具有小于第一掩模和第二掩模中的开口的开口。 然后，通过第四掩模进行第二深孔注入，以将第二类型的杂质植入到衬底的第二深度。

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