公开(公告)号：US09058455B2

公开(公告)日：2015-06-16

申请号：US13354705

申请日：2012-01-20

Applicant: James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/48 ,  H03H9/64 ,  H01L23/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/66 ,  H01L25/16

CPC classification number: H01L41/293 ,  G06F17/5063 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L25/16 ,  H01L27/0694 ,  H01L28/40 ,  H01L41/0815 ,  H01L41/25 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2225/06548 ,  H03H9/64

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract translation: 在半导体衬底的背面上的集成射频（RF）滤波器的设计结构包括：在衬底的第一侧上的器件; 在衬底的背面上的射频（RF）滤波器; 以及至少一个衬底导体，其从所述衬底的前侧延伸到所述衬底的所述背面并将所述RF滤波器电耦合到所述器件。

公开(公告)号：US20150041904A1

公开(公告)日：2015-02-12

申请号：US14493749

申请日：2014-09-23

Applicant: James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

Inventor： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/1041 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28026 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract translation: 一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。 此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

公开(公告)号：US08743247B2

公开(公告)日：2014-06-03

申请号：US12013826

申请日：2008-01-14

Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan

Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan

IPC: H04N3/14 ,  H01L31/062

CPC classification number: H01L31/103 ,  H04N5/353 ,  H04N5/374 ,  H04N5/3745

Abstract: A method of forming a CMOS active pixel sensor (APS) cell structure having at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.

Abstract translation: 一种形成具有至少一个传输栅极器件和操作方法的CMOS有源像素传感器（APS）单元结构的方法。 第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。 光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方 用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。 或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间 电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

公开(公告)号：US08610174B2

公开(公告)日：2013-12-17

申请号：US13307412

申请日：2011-11-30

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L31/109

CPC classification number: H01L29/66234 ,  H01L29/0826 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371

Abstract: Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.

Abstract translation: 公开了具有降低的集电极基座的晶体管，用于减小基极 - 集电极结电容。 凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列， 收集区域。 本征基层在凸起的收集器基座和介电层之上。 外在基层在本征基层之上。 因此，外部基极层和副集电极区域之间的空间增加。 该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。 因此，集电极结电容减小，因此最大振荡频率增加。

公开(公告)号：US08440490B2

公开(公告)日：2013-05-14

申请号：US13288686

申请日：2011-11-03

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Dale J. Pearson ,  Dennis L. Rogers

IPC: H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

Abstract: A method for manufacturing a pixel sensor cell that includes a photosensitive element having a non-laterally disposed charge collection region. The method includes forming a trench recess in a substrate of a first conductivity type material, and filling the trench recess with a material having second conductivity type material. The second conductivity type material is then diffused out of the filled trench material to the substrate region surrounding the trench to form the non-laterally disposed charge collection region. The filled trench material is removed to provide a trench recess, and the trench recess is filled with a material having a first conductivity type material. A surface implant layer is formed at either side of the trench having a first conductivity type material. A collection region of a trench-type photosensitive element is formed of the outdiffused second conductivity type material and is isolated from the substrate surface.

Abstract translation: 一种制造像素传感器单元的方法，该像素传感器单元包括具有非横向放置的电荷收集区域的感光元件。 该方法包括在第一导电类型材料的衬底中形成沟槽凹槽，并用具有第二导电类型材料的材料填充沟槽凹槽。 然后将第二导电类型材料从填充的沟槽材料扩散到围绕沟槽的衬底区域，以形成非横向布置的电荷收集区域。 去除填充的沟槽材料以提供沟槽凹槽，并且用具有第一导电类型材料的材料填充沟槽凹槽。 表面注入层形成在具有第一导电类型材料的沟槽的任一侧。 沟槽型感光元件的收集区域由向外扩散的第二导电型材料形成，并与衬底表面隔离。

公开(公告)号：US08039875B2

公开(公告)日：2011-10-18

申请号：US11850776

申请日：2007-09-06

Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC: H01L27/148 ,  H01L31/062

CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281 ,  H01L31/1037

Abstract: The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

Abstract translation: 本发明涉及一种像素传感器单元的设计结构。 像素传感器单元对于给定的光量大约使可用信号加倍。 具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上​​，以及p型收集阱区域 用于收集由撞击光子产生的孔的基板的表面。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US08003425B2

公开(公告)日：2011-08-23

申请号：US12120459

申请日：2008-05-14

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

IPC: H01L21/00

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

Abstract translation: 在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。 突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

公开(公告)号：US07772028B2

公开(公告)日：2010-08-10

申请号：US11959841

申请日：2007-12-19

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

IPC: H01L21/66

CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

Abstract: A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Abstract translation: CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US07759755B2

公开(公告)日：2010-07-20

申请号：US12120413

申请日：2008-05-14

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

IPC: H01L31/112 ,  H01L31/0216

CPC classification number: H01L31/103 ,  H01L24/05 ,  H01L24/73 ,  H01L27/14603 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1464 ,  H01L27/14643 ,  H01L31/02165 ,  H01L31/0236 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  Y02E10/50 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract translation: 提供了具有不同折射率的两层之间的突起阵列的光学结构。 突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。 突起的阵列提供了很少的反射光的高透射率。 突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

公开(公告)号：US07732845B2

公开(公告)日：2010-06-08

申请号：US12099339

申请日：2008-04-08

Applicant: James W Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

Inventor： James W Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

IPC: H01L31/062

CPC classification number: H01L27/14603

Abstract: A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.

Abstract translation: 在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力 连接源极区域和浮动漏极的方向。 拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。 因此CMOS图像传感器中的图像滞后减少。 此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强​​。