公开(公告)号：US06452863B2

公开(公告)日：2002-09-17

申请号：US09492982

申请日：2000-01-27

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C800

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling a memory device, wherein the memory device includes a plurality of memory cells. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Abstract translation: 一种控制存储器件的方法，其中存储器件包括多个存储器单元。 该方法包括向存储器件提供第一块大小信息，其中第一块大小信息定义响应于写请求由存储器件输入的第一数据量。 该方法还包括向存储器件发出写入请求，其中响应于写入请求，存储器件输入对应于第一块大小信息的第一数据量。

公开(公告)号：US6049846A

公开(公告)日：2000-04-11

申请号：US161090

申请日：1998-09-25

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal.

Abstract translation: 一种具有至少一个包括多个存储单元的存储器部分的同步存储器件。 存储器件包括时钟接收器电路，时钟产生电路和输入接收器电路。 时钟接收器电路从外部总线接收外部时钟信号。 时钟发生电路耦合到时钟接收器电路，并且包括延迟锁定环路以产生第一内部时钟信号。 输入接收器电路耦合到时钟产生电路和外部总线，以响应于第一内部时钟信号从外部总线采样信息。

公开(公告)号：US6044426A

公开(公告)日：2000-03-28

申请号：US239522

申请日：1999-01-29

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: A memory system having a plurality of memory devices, each having at least one memory array which includes a plurality of memory cells. The memory system comprises a bus, a controller, a first memory device, and a second memory device. The bus includes a plurality of sisal lines coupled to the plurality of memory devices. The bus provides a transaction request including identification information generated by the controller, to the plurality of memory devices. The first and second memory device each include a programmable register, interface circuitry, and comparison circuitry. The interface circuitry of each memory device may store a memory identification value to identify each memory device on the bus. The interface circuitry of each memory device is coupled to the bus to receive a transaction request. The comparison circuitry of each memory device is coupled to the programmable register and the interface circuitry to determine whether the identification information in the transaction request corresponds to the memory identification value wherein when the identification information corresponds to a memory identification value, that memory device responds to the transaction request.

Abstract translation: 一种具有多个存储器件的存储器系统，每个存储器件具有包括多个存储器单元的至少一个存储器阵列。 存储器系统包括总线，控制器，第一存储器件和第二存储器件。 总线包括耦合到多个存储器件的多个剑麻线。 总线提供包括由控制器生成的识别信息的交易请求到多个存储器装置。 第一和第二存储器件各自包括可编程寄存器，接口电路和比较电路。 每个存储器件的接口电路可以存储存储器标识值以识别总线上的每个存储器件。 每个存储器件的接口电路被耦合到总线以接收事务请求。 每个存储器件的比较电路耦合到可编程寄存器和接口电路，以确定事务请求中的识别信息是否对应于存储器标识值，其中当识别信息对应于存储器标识值时，该存储器件响应于 交易请求。

公开(公告)号：US6032214A

公开(公告)日：2000-02-29

申请号：US252998

申请日：1999-02-19

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention is directed to a method of operating a memory device wherein the memory device includes a plurality of memory cells. The method comprises providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be output onto a bus in response to a read request. The method further includes issuing a first read request to the memory device, wherein in response to the first read request, the memory device outputs the first amount of data corresponding to the first block size information onto the bus synchronously with respect to a first external clock signal and a second external clock signal. In one preferred embodiment, the method may further include providing a code which is representative of a number of clock cycles of the first and second external clock which are to transpire before data is output by the memory device onto the bus. The memory device stores the code in a programmable register on the memory device. In this preferred embodiment, the first amount of data corresponding to the first block size information is output after the number of clock cycles of the first and second external clock transpire. The number of clock cycles may be a whole number or a fraction.

Abstract translation: 本发明涉及一种操作存储器件的方法，其中存储器件包括多个存储器单元。 该方法包括向存储器设备提供第一块大小信息，其中响应于读请求，第一块大小信息定义要输出到总线上的第一数据量。 该方法还包括向存储器件发出第一读取请求，其中响应于第一读取请求，存储器件相对于第一外部时钟同步地将与第一块大小信息相对应的第一数据量数据输出到总线上 信号和第二个外部时钟信号。 在一个优选实施例中，该方法可以进一步包括提供代表在数据由存储器件输出到总线上之前要发出的第一和第二外部时钟的数量的时钟周期的代码。 存储器件将代码存储在存储器件上的可编程寄存器中。 在该优选实施例中，在第一外部时钟和第二外部时钟的时钟周期数出现之后输出对应于第一块大小信息的第一数据量。 时钟周期的数量可以是整数或分数。

公开(公告)号：US5995443A

公开(公告)日：1999-11-30

申请号：US262114

申请日：1999-03-04

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/006 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：US5915105A

公开(公告)日：1999-06-22

申请号：US979127

申请日：1997-11-26

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1/10 ,  G06F11/00 ,  G06F11/10 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F13/376 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G06F11/1048 ,  G11C2207/105 ,  G11C2207/108 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：US08966413B2

公开(公告)日：2015-02-24

申请号：US13399770

申请日：2012-02-17

Applicant: Ofer Shacham ,  Mark Horowitz ,  Stephen Richardson

Inventor： Ofer Shacham ,  Mark Horowitz ,  Stephen Richardson

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.

Abstract translation: 根据本发明实施例的芯片发生器将设计者的知识和设计权衡编成可用于创建许多不同芯片的模板。 像可重构设计一样，本发明的实施例解决了顶级系统架构，分摊软件和验证和设计成本，并为应用程序开发人员提供了丰富的系统仿真环境。 同时，在顶层以下，开发人员可以“编程”架构的各个内部组件。 与可重构芯片不同，根据本发明的实施例的芯片发生器编译程序以创建定制的芯片。 这种编译过程在制造硅之前的时间很长。 结果是一个框架，可以在架构层面实现更多的定制生成的芯片，因为如果定制过程需要可以添加额外的组件和逻辑。

公开(公告)号：US07736282B1

公开(公告)日：2010-06-15

申请号：US11805118

申请日：2007-05-22

Applicant: Mark Horowitz

Inventor： Mark Horowitz

IPC: A63B22/06 ,  A63B69/16

CPC classification number: A63B69/16 ,  A63B2069/162 ,  A63B2069/163 ,  A63B2069/164 ,  A63B2069/167 ,  A63B2210/50

Abstract: Method and apparatus for allowing a person with disabilities to learn to pedal a conventional bicycle which device also converts a conventional bicycle into an in-place exercise bike. In the bike trainer embodiment, the device allows the training wheels which are attached to the rear wheel of a bicycle to be elevated by being placed in a right and left trough of the base of the device so that the rear wheel of the bicycle is elevated off the ground and spins freely in a space between the right and left troughs. In the exercise bicycle embodiment, an adjustable rear roller assembly can be attached to the base of the device so that the rear wheel of the bicycle rests on a pair of rollers so as to allow the rear wheel of the bicycle to contact and roll on a front and rear roller so as to increase pedaling resistance while the front wheel of the bicycle is stabilized by a stand having a pair of adjustable upright members and a pair of laterally extending members for maintaining the bicycle in a stable position. Other embodiments are also disclosed.

Abstract translation: 允许残疾人学习踏上传统自行车的方法和装置，该装置还将常规自行车转换成就地运动自行车。 在自行车训练器实施例中，该装置允许通过将装在自行车的后轮上的训练轮放置在装置的底座的左右槽中使自行车的后轮升高 离开地面，并在右侧和左侧槽间空间自由旋转。 在运动自行车实施例中，可调整的后轮组件可以附接到装置的基座，使得自行车的后轮搁在一对辊上，以便允许自行车的后轮接触和滚动 前轮和后轮，以便通过具有一对可调直立部件和一对横向延伸部件的支架使自行车的前轮稳定在稳定的位置，从而增加踏板阻力。 还公开了其他实施例。

公开(公告)号：US07456778B2

公开(公告)日：2008-11-25

申请号：US11393104

申请日：2006-03-29

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: H03M1/00 ,  H03M7/00

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract translation: 用于多电平电流模式驱动器的电流控制器。 电流控制器包括多电平电压基准和至少一个源校准信号。 比较器通过耦合网络耦合到多电平电压基准和至少一个源校准信号。 从多电平参考电压施加所选择的电压，并且将所选择的源校准信号从至少一个源校准信号施加到比较器。

公开(公告)号：US20070080718A1

公开(公告)日：2007-04-12

申请号：US11538333

申请日：2006-10-03

Applicant: Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: H03K19/094

CPC classification number: H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract translation: 具有自适应发送预加重的高速信号系统。 发射电路具有多个输出驱动器，以将第一信号输出到信号路径上。 接收电路被耦合以经由信号路径接收第一信号并被配置为生成第一信号是否超过阈值电平的指示。 第一阈值控制电路被耦合以从接收电路接收指示，并且被配置为根据第一信号是否超过阈值电平来调整阈值电平。 驱动强度控制电路被耦合以从接收电路接收指示，并且被配置为根据第一信号是否超过阈值电平来调整多个输出驱动器中的至少一个输出驱动器的驱动强度。