公开(公告)号：US08966413B2

公开(公告)日：2015-02-24

申请号：US13399770

申请日：2012-02-17

Applicant: Ofer Shacham ,  Mark Horowitz ,  Stephen Richardson

Inventor： Ofer Shacham ,  Mark Horowitz ,  Stephen Richardson

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A chip generator according to an embodiment of the present invention codifies designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, an embodiment of the present invention fixes the top level system architecture, amortizes software and validation and design costs, and enables a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can “program” the individual inner components of the architecture. Unlike reconfigurable chips, a chip generator according to an embodiment of the present invention, compiles the program to create a customized chip. This compilation process occurs at elaboration time—long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level because additional components and logic can be added if the customization process requires it.

Abstract translation: 根据本发明实施例的芯片发生器将设计者的知识和设计权衡编成可用于创建许多不同芯片的模板。 像可重构设计一样，本发明的实施例解决了顶级系统架构，分摊软件和验证和设计成本，并为应用程序开发人员提供了丰富的系统仿真环境。 同时，在顶层以下，开发人员可以“编程”架构的各个内部组件。 与可重构芯片不同，根据本发明的实施例的芯片发生器编译程序以创建定制的芯片。 这种编译过程在制造硅之前的时间很长。 结果是一个框架，可以在架构层面实现更多的定制生成的芯片，因为如果定制过程需要可以添加额外的组件和逻辑。

公开(公告)号：US07736282B1

公开(公告)日：2010-06-15

申请号：US11805118

申请日：2007-05-22

Applicant: Mark Horowitz

Inventor： Mark Horowitz

IPC: A63B22/06 ,  A63B69/16

CPC classification number: A63B69/16 ,  A63B2069/162 ,  A63B2069/163 ,  A63B2069/164 ,  A63B2069/167 ,  A63B2210/50

Abstract: Method and apparatus for allowing a person with disabilities to learn to pedal a conventional bicycle which device also converts a conventional bicycle into an in-place exercise bike. In the bike trainer embodiment, the device allows the training wheels which are attached to the rear wheel of a bicycle to be elevated by being placed in a right and left trough of the base of the device so that the rear wheel of the bicycle is elevated off the ground and spins freely in a space between the right and left troughs. In the exercise bicycle embodiment, an adjustable rear roller assembly can be attached to the base of the device so that the rear wheel of the bicycle rests on a pair of rollers so as to allow the rear wheel of the bicycle to contact and roll on a front and rear roller so as to increase pedaling resistance while the front wheel of the bicycle is stabilized by a stand having a pair of adjustable upright members and a pair of laterally extending members for maintaining the bicycle in a stable position. Other embodiments are also disclosed.

Abstract translation: 允许残疾人学习踏上传统自行车的方法和装置，该装置还将常规自行车转换成就地运动自行车。 在自行车训练器实施例中，该装置允许通过将装在自行车的后轮上的训练轮放置在装置的底座的左右槽中使自行车的后轮升高 离开地面，并在右侧和左侧槽间空间自由旋转。 在运动自行车实施例中，可调整的后轮组件可以附接到装置的基座，使得自行车的后轮搁在一对辊上，以便允许自行车的后轮接触和滚动 前轮和后轮，以便通过具有一对可调直立部件和一对横向延伸部件的支架使自行车的前轮稳定在稳定的位置，从而增加踏板阻力。 还公开了其他实施例。

公开(公告)号：US07456778B2

公开(公告)日：2008-11-25

申请号：US11393104

申请日：2006-03-29

Applicant: Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

Inventor： Carl Werner ,  Mark Horowitz ,  Pak Chau ,  Scott Best ,  Stefanos Sidiropoulos

IPC: H03M1/00 ,  H03M7/00

CPC classification number: H04L25/4917 ,  G06F13/1678 ,  G06F13/4068 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/10 ,  G11C11/56 ,  G11C27/02 ,  G11C2207/108 ,  H04L7/0331 ,  H04L7/0332 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0296 ,  H04L25/0298 ,  H04L25/03006 ,  H04L25/03057 ,  H04L25/08 ,  H04L25/4902

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract translation: 用于多电平电流模式驱动器的电流控制器。 电流控制器包括多电平电压基准和至少一个源校准信号。 比较器通过耦合网络耦合到多电平电压基准和至少一个源校准信号。 从多电平参考电压施加所选择的电压，并且将所选择的源校准信号从至少一个源校准信号施加到比较器。

公开(公告)号：US20070080718A1

公开(公告)日：2007-04-12

申请号：US11538333

申请日：2006-10-03

Applicant: Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: H03K19/094

CPC classification number: H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract translation: 具有自适应发送预加重的高速信号系统。 发射电路具有多个输出驱动器，以将第一信号输出到信号路径上。 接收电路被耦合以经由信号路径接收第一信号并被配置为生成第一信号是否超过阈值电平的指示。 第一阈值控制电路被耦合以从接收电路接收指示，并且被配置为根据第一信号是否超过阈值电平来调整阈值电平。 驱动强度控制电路被耦合以从接收电路接收指示，并且被配置为根据第一信号是否超过阈值电平来调整多个输出驱动器中的至少一个输出驱动器的驱动强度。

公开(公告)号：US20060277434A1

公开(公告)日：2006-12-07

申请号：US11145429

申请日：2005-06-03

Applicant: Ely Tsern ,  Mark Horowitz ,  Frederick Ware

Inventor： Ely Tsern ,  Mark Horowitz ,  Frederick Ware

IPC: G06F11/00

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0745 ,  G06F11/0766 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G06F11/20 ,  G11C29/52 ,  H03M13/03 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

公开(公告)号：US20060250160A1

公开(公告)日：2006-11-09

申请号：US11456332

申请日：2006-07-10

Applicant: Kun-Yung Chang ,  Mark Horowitz

Inventor： Kun-Yung Chang ,  Mark Horowitz

IPC: G01R13/00 ,  H03K19/00 ,  G01R29/26 ,  H01L25/00

CPC classification number: G06F1/06

Abstract: A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has occurred and, if so, to assert a hold signal. The locked loop circuit responds to assertion of the hold signal by transitioning to a second operating mode in which the phase of the second clock signal is not adjusted.

Abstract translation: 一个容错时钟发生电路。 提供第一和第二时钟信号发生器以产生第一和第二时钟信号。 第二时钟信号发生器包括锁定环路电路，其在第一操作模式中根据需要调整第二时钟信号的相位，以维持第一和第二时钟信号之间的相位对准。 提供故障检测电路以确定是否发生了与第一时钟信号的产生有关的故障，并且如果是，则断言保持信号。 锁定环电路通过转换到第二时钟信号的相位未被调整的第二操作模式来响应保持信号的断言。

公开(公告)号：US07110322B2

公开(公告)日：2006-09-19

申请号：US10939501

申请日：2004-09-14

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G11C8/00

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module including an integrated circuit is disclosed. In one particular exemplary embodiment, the memory module may comprise a plurality of memory devices and an integrated circuit device that is coupled to the plurality of memory devices. The integrated circuit device includes a first circuit to receive control information specifying a write operation, and address information specifying a memory location corresponding to the write operation, wherein the memory location is in a first memory device of the plurality of memory devices, and wherein the control information and the address information are received in a multiplexed format. The integrated circuit device also includes a second circuit, including a plurality of output drivers, to output data after a first number of clock cycles of an external clock signal transpire, wherein the data is to be written to the first memory device during the write operation.

Abstract translation: 公开了一种包括集成电路的存储模块。 在一个特定的示例性实施例中，存储器模块可以包括多个存储器件和耦合到多个存储器件的集成电路器件。 集成电路装置包括：第一电路，用于接收指定写入操作的控制信息;以及地址信息，其指定对应于写入操作的存储器位置，其中存储器位置在多个存储器件的第一存储器件中，并且其中 以多路复用格式接收控制信息和地址信息。 集成电路装置还包括包括多个输出驱动器的第二电路，用于在外部时钟信号的第一数量的时钟周期发生之后输出数据，其中在写入操作期间将数据写入第一存储器件 。

公开(公告)号：US20050201164A1

公开(公告)日：2005-09-15

申请号：US11123931

申请日：2005-05-06

Applicant: Richard Barth ,  Mark Horowitz ,  Craig Hampel ,  Frederick Ware

Inventor： Richard Barth ,  Mark Horowitz ,  Craig Hampel ,  Frederick Ware

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

Abstract: An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates a mode of operation of the integrated circuit memory device. The mode of operation is selected from at least one of a synchronous mode of operation and an asynchronous mode of operation. During the synchronous mode of operation, the circuit outputs the data in response to a transition of an external clock signal. During the asynchronous mode of operation, the circuit outputs the data after a period of time from when a transition of an external control signal is detected.

Abstract translation: 集成电路存储器件包括用于存储数据的存储器阵列，用于在引脚处输出数据的电路以及用于存储指示集成电路存储器件的操作模式的值的寄存器。 操作模式从同步操作模式和异步操作模式中的至少一个中选择。 在同步操作模式期间，电路响应于外部时钟信号的转变而输出数据。 在异步操作模式期间，电路在检测到外部控制信号的转变之后的一段时间后输出数据。

公开(公告)号：US20050134305A1

公开(公告)日：2005-06-23

申请号：US10740087

申请日：2003-12-17

Applicant: Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

Inventor： Vladimir Stojanovic ,  Andrew Ho ,  Anthony Bessios ,  Fred Chen ,  Elad Alon ,  Mark Horowitz

IPC: H03K19/003 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04L25/49

CPC classification number: H04L25/49 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0416 ,  H04L25/025 ,  H04L25/028 ,  H04L25/0282 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/4917 ,  H04L2025/03363 ,  H04L2025/03802

Abstract: A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling circuit samples the first signal to determine whether the first signal exceeds a second threshold. The drive strength of the output driver circuit is adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds, and the second threshold is adjusted based, at least in part, on whether the first signal exceeds the second threshold.

Abstract translation: 一种具有第一和第二采样电路和输出驱动电路的信号系统。 第一采样电路对由输出驱动器电路产生的第一信号进行采样，以确定第一信号是否超过第一阈值。 第二采样电路对第一信号进行采样以确定第一信号是否超过第二阈值。 至少部分地基于第一信号是否超过第一和第二阈值来调整输出驱动器电路的驱动强度，并且至少部分地基于第一信号是否超过第二信号来调整第二阈值 阈。

公开(公告)号：US06807598B2

公开(公告)日：2004-10-19

申请号：US10054196

申请日：2002-01-22

Applicant: Michael Farmwald ,  Mark Horowitz

Inventor： Michael Farmwald ,  Mark Horowitz

IPC: G06F1300

CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/04 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108

Abstract: A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal. A second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal. In addition, the integrated circuit device includes a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.

Abstract translation: 一种同步集成电路装置，包括用于接收外部时钟信号的时钟接收器和用于输出数据的多个输出驱动器。 相对于外部时钟信号的上升沿转换，数据的第一部分被同步地输出。 相对于外部时钟信号的下降沿转换，数据的第二部分被同步地输出。 此外，集成电路器件包括耦合到多个输出驱动器和时钟接收器的延迟锁定环，以使数据的第一和第二部分的输出与外部时钟信号同步。