公开(公告)号：US20060261403A1

公开(公告)日：2006-11-23

申请号：US11135002

申请日：2005-05-23

申请人： Franz Hofmann ,  Johannes Luyken ,  Michael Specht

发明人： Franz Hofmann ,  Johannes Luyken ,  Michael Specht

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42352 ,  H01L29/66833

摘要： An array of charge-trapping memory cells and pluralities of parallel wordlines and parallel bitlines running transversely to the wordlines are arranged on a substrate surface. Gate electrodes are located between the wordlines and bitlines and are, in their sequence along the direction of the wordlines, connected alternatingly to one of two adjacent wordlines.

摘要翻译： 电荷俘获存储器单元阵列和横向于字线的并行字线和并行位线的多个排列在衬底表面上。 栅电极位于字线和位线之间，并且沿着字线方向的顺序交替地连接到两个相邻字线之一。

公开(公告)号：US20060181925A1

公开(公告)日：2006-08-17

申请号：US11283572

申请日：2005-11-18

申请人： Michael Specht ,  Franz Hofmann ,  Ulrich Dorda ,  Johannes Kretz ,  Lars Dreeskornfeld

发明人： Michael Specht ,  Franz Hofmann ,  Ulrich Dorda ,  Johannes Kretz ,  Lars Dreeskornfeld

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.

摘要翻译： 存储晶体管被布置成多个行和列。 第一列的每个存储晶体管的第一源极/漏极端子连接到第一金属化平面中的导电导体轨道，并且与第一列相邻的第二列的每个存储晶体管的第一源极/漏极端子被连接 到第二金属化平面中的导电导体轨道。

公开(公告)号：US20060175666A1

公开(公告)日：2006-08-10

申请号：US11324803

申请日：2006-01-03

申请人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht

发明人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/78 ,  Y10S438/964

摘要： An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

公开(公告)号：US20050269617A1

公开(公告)日：2005-12-08

申请号：US10523944

申请日：2003-09-13

申请人： Franz Hofmann ,  Volker Lehmann ,  Lothar Risoh ,  Wolfgang Rosner ,  Michael Specht

发明人： Franz Hofmann ,  Volker Lehmann ,  Lothar Risoh ,  Wolfgang Rosner ,  Michael Specht

IPC分类号： H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1203 ,  H01L28/82 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.

摘要翻译： 提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。 形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

公开(公告)号：US20050199913A1

公开(公告)日：2005-09-15

申请号：US11074345

申请日：2005-03-07

申请人： Franz Hofmann ,  Thomas Schulz ,  Michael Specht

发明人： Franz Hofmann ,  Thomas Schulz ,  Michael Specht

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： The invention relates to a semiconductor memory having a multiplicity of fins made of semiconductor material which are spaced apart from one another, a multiplicity of channel regions and contact regions being formed in each of the fins, a multiplicity of word lines, a multiplicity of storage layers, at least one of the storage layers being arranged between each of the channel regions and the word line, and a multiplicity of bit lines, the longitudinal axes of first bit line portions running parallel to a first bit line direction and the longitudinal axes of second bit line portions running parallel to a second bit line direction, the second bit line direction being rotated relative to the first bit line direction, each of the bit lines being electrically connected to a multiplicity of the contact regions, wherein, between two contact regions of the same fin that are connected to one of the bit lines, a contact region is not connected to the respective bit line.

摘要翻译： 本发明涉及一种半导体存储器，其具有由半导体材料制成的多个鳍片，它们彼此间隔开，多个通道区域和接触区域形成在每个鳍片中，多个字线，多个存储器 存储层中的至少一个布置在每个沟道区域和字线之间，并且多个位线，第一位线部分的纵向轴线平行于第一位线方向延伸，并且纵向轴线 第二位线部分平行于第二位线方向延伸，第二位线方向相对于第一位线方向旋转，每个位线电连接到多个接触区域，其中在两个接触区域之间 与位线之一连接的相同的鳍片，接触区域不连接到相应的位线。

公开(公告)号：US20050139893A1

公开(公告)日：2005-06-30

申请号：US10991345

申请日：2004-11-09

申请人： Franz Hofmann ,  Erhard Landgraf ,  Wolfgang Rosner ,  Michael Specht ,  Martin Staedele

发明人： Franz Hofmann ,  Erhard Landgraf ,  Wolfgang Rosner ,  Michael Specht ,  Martin Staedele

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L21/8242 ,  H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.

摘要翻译： 在半导体存储器中，在由半导体材料制成的翅片的相应顶侧上存在多个具有捕获层或浮栅电极作为存储介质的FinFET布置。 栅电极的材料也存在于翅片的两个侧壁上，以便形成侧壁晶体管，并且在栅电极之间形成属于相应鳍片的字线的部分。

公开(公告)号：US20050048720A1

公开(公告)日：2005-03-03

申请号：US10926838

申请日：2004-08-25

申请人： Andrew Graham ,  Franz Hofmann ,  Michael Specht

发明人： Andrew Graham ,  Franz Hofmann ,  Michael Specht

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/66825

摘要： Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.

摘要翻译： 具有具有第一和第二源极/漏极区域的第一层和布置在第一和第二源极/漏极区域之间和之后的沟道区域的浮动栅极存储单元以及布置在第一层上的浮动栅极层，其中第一和第二 源极/漏极区域和浮置栅极层由金属导电材料形成，并且沟道区域由电绝缘材料形成。

公开(公告)号：US09057138B2

公开(公告)日：2015-06-16

申请号：US13263940

申请日：2010-04-09

申请人： Bernd Stuermer ,  Volkmar Frick ,  Michael Specht ,  Michael Sterner ,  Berthold Hahn ,  Ulrich Zuberbuehler

发明人： Bernd Stuermer ,  Volkmar Frick ,  Michael Specht ,  Michael Sterner ,  Berthold Hahn ,  Ulrich Zuberbuehler

IPC分类号： F03B13/00 ,  C25B1/04 ,  C10L3/08 ,  C12M1/107 ,  C12M1/00

CPC分类号： C25B1/04 ,  C10L3/08 ,  C12M21/04 ,  C12M43/00 ,  C12M43/08 ,  C25B15/08 ,  Y02E50/343 ,  Y02E60/324 ,  Y02E60/366 ,  Y02P20/129 ,  Y02P20/133 ,  Y02P20/134

摘要： An energy supply system is provided with an electricity generating device for regeneratively generating electrical energy that can be fed into an electricity supply grid. The energy supply system includes an electricity generating device for regeneratively generating electrical energy which can be fed into an electricity supply grid, a hydrogen generating device for generating hydrogen using electrical energy from the regenerative electricity generating device, a methanation device for converting hydrogen generated by the hydrogen generating device and a supplied carbon oxide gas into a gas containing methane, and a gas providing device for providing a supplementary gas or a replacement gas in a variably specifiable supplementary/replacement gas quality suitable for feeding into a gas supply grid with the use of the gas containing methane from the methanation device and/or the hydrogen from the hydrogen generating device. A method of operating the system is also provided.

摘要翻译： 能量供给系统具有用于再生发电的发电装置，该电能可供给到供电电网。 能量供给系统包括用于再生发电的发电装置，其可以供给到供电电网;氢发生装置，其使用来自再生发电装置的电能产生氢;甲烷化装置，用于将由 氢气生成装置和供给的碳氧化物气体组装成含有甲烷的气体，以及气体提供装置，用于以可变形式指定的补充/替换气体质量提供补充气体或替代气体，该气体适合于通过使用 含有来自甲烷化装置的甲烷的气体和/或来自氢生成装置的氢气。 还提供了一种操作该系统的方法。

公开(公告)号：US20130041051A1

公开(公告)日：2013-02-14

申请号：US13517941

申请日：2010-11-11

申请人： Ulrich Zuberbuhler ,  Bernd Sturmer ,  Volkmar Frick ,  Michael Specht ,  Martin Buxbaum

发明人： Ulrich Zuberbuhler ,  Bernd Sturmer ,  Volkmar Frick ,  Michael Specht ,  Martin Buxbaum

IPC分类号： C07C1/12 ,  B01J19/00

CPC分类号： B01J19/0006 ,  B01J8/001 ,  B01J8/067 ,  B01J19/249 ,  B01J2208/00256 ,  B01J2208/00274 ,  B01J2208/025 ,  B01J2219/0004 ,  B01J2219/0006 ,  B01J2219/00063 ,  B01J2219/00065 ,  B01J2219/00108 ,  B01J2219/00162 ,  B01J2219/00202 ,  B01J2219/00213 ,  B01J2219/00231 ,  B01J2219/00236 ,  B01J2219/00238 ,  B01J2219/0024 ,  C07C1/12 ,  C10L3/08 ,  C07C9/04

摘要： The invention relates to a method for producing a methane-rich product gas, in which a starting gas containing hydrogen and carbon dioxide is catalytically methanated under the influence of at least one adjustatable parameter in at least two stages and at least one criterion relating to the composition of the product gas is monitored. The criterion is fulfilled under a condition influencing the method and when the condition changes, a change in the parameter setting that preserves fulfilment of the criterion is affected.

摘要翻译： 本发明涉及一种生产富含甲烷的产物气体的方法，其中含有氢气和二氧化碳的起始气体在至少两个阶段的至少一个可调节参数的影响下被催化甲烷化，并且至少有一个与 监测产品气体的组成。 该条件在影响该方法的条件下实现，当条件变化时，影响到保持条件满足的参数设置的变化。

公开(公告)号：US07709827B2

公开(公告)日：2010-05-04

申请号：US10533550

申请日：2003-10-29

申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Hönlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Johannes Richard Luyken ,  Wolfgang Rösner ,  Thomas Schulz ,  Michael Specht

发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Hönlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Johannes Richard Luyken ,  Wolfgang Rösner ,  Thomas Schulz ,  Michael Specht

IPC分类号： H01L21/8238

CPC分类号： H01L29/78642 ,  B82Y10/00 ,  H01L27/283 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/775 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

摘要翻译： 本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。 垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。 纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。 中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。