公开(公告)号：US20100164116A1

公开(公告)日：2010-07-01

申请号：US12344838

申请日：2008-12-29

Applicant: Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

Inventor： Baozhen Li ,  Paul S. McLaughlin ,  Timothy D. Sullivan

IPC: H01L23/52 ,  H01L21/4763 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

Abstract translation: 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。

公开(公告)号：US20100038780A1

公开(公告)日：2010-02-18

申请号：US12190612

申请日：2008-08-13

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Marie-Claude Paquet ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/743 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract translation: 底部填充流动引导结构及其使用方法具有模块。 特别地，底部填充流动引导结构与基底一体化并且被构造成防止在毛细管底部填充过程期间发生空气滞留。

公开(公告)号：US07601602B2

公开(公告)日：2009-10-13

申请号：US11481514

申请日：2006-07-06

Applicant: John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

Inventor： John M. Aitken ,  Fen Chen ,  Timothy D. Sullivan

IPC: H01L21/04

CPC classification number: H01L28/20 ,  H01L27/101

Abstract: An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

Abstract translation: 一种片上超小型可编程半导体电阻器件及器件结构及其制造方法。 每个半导体电阻器件结构由表现出精确电阻值的一个或多个导电连接的埋沟槽型电阻器元件形成。 至少两个半导体电阻器件结构可以通过一个或多个保险丝器件的中间串联或并联配置连接，该熔丝器件可以被吹制以实现期望的总电阻值。

公开(公告)号：US20090230555A1

公开(公告)日：2009-09-17

申请号：US12049698

申请日：2008-03-17

Applicant: Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

Inventor： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract translation: 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 一种金属层堆叠，包括从底部到顶部的低氧反应性金属层，底部过渡金属层，底部过渡金属氮化物层，铝 - 铜层，任选的顶部过渡金属层和顶部过渡层 金属氮化物层。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成，因此提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

公开(公告)号：US20090183131A1

公开(公告)日：2009-07-16

申请号：US12050990

申请日：2008-03-19

Applicant: Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

Inventor： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

IPC: G06F17/50

CPC classification number: H01L23/345 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

Abstract translation: 公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

公开(公告)号：US07511378B2

公开(公告)日：2009-03-31

申请号：US11442911

申请日：2006-05-30

Applicant: Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

Inventor： Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

IPC: H01L23/48

CPC classification number: G06F17/5077 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/0005 ,  H01L2924/00

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Abstract translation: 具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。 该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。 由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。 第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。 第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

公开(公告)号：US07470613B2

公开(公告)日：2008-12-30

申请号：US11619748

申请日：2007-01-04

Applicant: Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

Inventor： Birendra N. Agarwala ,  Eric M. Coker ,  Anthony Correale, Jr. ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Richard A. Wachnik

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

Abstract translation: 一种用于形成互连结构的方法，所述互连结构包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下导电衬垫在侧面和底部 的下层电线; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

公开(公告)号：US20080297188A1

公开(公告)日：2008-12-04

申请号：US11755827

申请日：2007-05-31

Applicant: Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

Inventor： Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/2875 ,  G01R31/2879

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.

Abstract translation: 公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。 该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

公开(公告)号：US07445966B2

公开(公告)日：2008-11-04

申请号：US11160468

申请日：2005-06-24

Applicant: John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Timothy D. Sullivan ,  Steven H. Voldman

IPC: H01L23/60

CPC classification number: H01L27/0248 ,  Y10S438/926

Abstract: A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract translation: 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

公开(公告)号：US20080231312A1

公开(公告)日：2008-09-25

申请号：US12154304

申请日：2008-05-22

Applicant: Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

Inventor： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Abstract translation: 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。