公开(公告)号：US20170117185A1

公开(公告)日：2017-04-27

申请号：US15402192

申请日：2017-01-09

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： William John NELSON ,  Nathapong SUTHIWONGSUNTHORN ,  Beng Yeung HO ,  Poh Leng Wilson ONG

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/308 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/268 ,  H01L23/544 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/14 ,  H01L2223/54453 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

公开(公告)号：US09564387B2

公开(公告)日：2017-02-07

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。

公开(公告)号：US20160104626A1

公开(公告)日：2016-04-14

申请号：US14881181

申请日：2015-10-13

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： William John NELSON ,  Nathapong SUTHIWONGSUNTHORN ,  Beng Yeung HO ,  Poh Leng Wilson ONG

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/14 ,  H01L2223/54453 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

Abstract translation: 介绍了切割晶片的方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片在主要器件区域上由多个管芯制成并且通过晶片的第一主表面上的切割通道彼此间隔开。 在晶片的第一或第二主表面上提供膜。 薄膜至少覆盖对应于主要装置区域的区域。 该方法还包括使用该膜作为蚀刻掩模和等离子体通过晶片的暴露的半导体材料蚀刻晶片以形成间隙，以将晶片上的多个管芯分离成多个单独的管芯。

公开(公告)号：US12302657B2

公开(公告)日：2025-05-13

申请号：US17664510

申请日：2022-05-23

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Emmanuel Espiritu ,  Il Kwon Shim ,  Jeffrey Punzalan ,  Teddy Joaquin Carreon

IPC: H01L27/146 ,  H01L23/31 ,  H10F39/00

Abstract: A semiconductor device has a substrate. A semiconductor die including a photosensitive circuit is disposed over the substrate. A shield is disposed over the substrate and semiconductor die with a first opening of the shield disposed over the photosensitive circuit. An outer section of the shield is attached to the substrate and includes a second opening. An encapsulant is deposited over the substrate and semiconductor die. The encapsulant extends into the first opening and a first area between the shield and substrate while a second area over the photosensitive circuit remains devoid of the encapsulant.

公开(公告)号：US20250079261A1

公开(公告)日：2025-03-06

申请号：US18818632

申请日：2024-08-29

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： IL Kwon SHIM ,  Roel Adeva ROBLES

IPC: H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065

Abstract: The present disclosure is directed to improving heat dissipation to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. The package includes at least primary and secondary heat dissipators to improve heat dissipation. In some embodiments, the package includes a tertiary heat dissipator to further improve heat dissipation.

公开(公告)号：US20250038037A1

公开(公告)日：2025-01-30

申请号：US18393621

申请日：2023-12-21

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： IL KWON SHIM ,  Dzafir Bin Mohd Shariff ,  Ronnie M. De Villa ,  Enrique E. SARILE, JR. ,  Chee Kay Chow ,  Jackson Fernandez Rosario ,  Chan Loong Neo

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/687

Abstract: Lamination systems and methods of fabricating devices are disclosed. The lamination system includes multiple processing modules for delaminating a backgrinding (BG) from a surface of the wafer and laminating a dicing tape on the surface of the wafer. The system includes a wafer receiving module which is configured to hold the wafer in place with a position chuck throughout the delamination and lamination process. By using a single positioning chuck, more efficient processing is achieved. For example, there is no need to re-lign the wafer when it is moved from one chuck to another.

公开(公告)号：US12211863B2

公开(公告)日：2025-01-28

申请号：US17394365

申请日：2021-08-04

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Il Kwon Shim ,  Jeffrey Punzalan ,  Emmanuel Espiritu ,  Allan Ilagan ,  Teddy Joaquin Carreon

IPC: H01L27/14 ,  H01L23/00 ,  H01L27/146

Abstract: A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

公开(公告)号：US20240234195A9

公开(公告)日：2024-07-11

申请号：US18490741

申请日：2023-10-19

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Chee Kay Chow ,  Zong Xiang Cai ,  Wei Ming Xian ,  Yao Hong Wu ,  Wing Keung Lam

IPC: H01L21/683 ,  H01L21/48 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/6838 ,  H01L21/4867 ,  H01L21/6715 ,  H01L21/67259 ,  H01L21/67736 ,  H01L21/67742 ,  H01L21/67766

Abstract: A manufacturing system includes a substrate disposed on a conveyer system. The conveyer system includes a pair of side supports. The substrate is moved on the conveyer system until the substrate is disposed over a bottom support block. The bottom support block is raised to physically contact the substrate. A transfer arm module is provided. The transfer arm module includes a flat bottom surface and an opening formed in the flat bottom surface. The transfer arm module is disposed with the flat bottom surface physically contacting the substrate opposite the bottom support block. A vacuum is enabled through the opening of the transfer arm module. The substrate is lifted off the bottom support block using the vacuum. The substrate is moved over a printing pallet using the transfer arm module. The vacuum is disabled when the substrate is in a positioning area of the printing pallet.

公开(公告)号：US12021096B2

公开(公告)日：2024-06-25

申请号：US17342546

申请日：2021-06-09

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Dennis Fernandez Tresnado ,  Mario Arwin Simon Fabian ,  Wedanni Linsangan Micla ,  Allan Pumatong Ilagan

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/10 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L23/04 ,  H01L23/10 ,  H01L23/562 ,  H01L24/32 ,  H01L27/14683 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/73265

Abstract: Semiconductor packages and methods for forming thereof are disclosed. The semiconductor package includes a package substrate having a die attach region with a die attached thereto. A protective cover is disposed over a sensor region of the die and attached to the die by a cover adhesive. The cover adhesive may serve as a standoff structure to support the protective cover. The standoff structure may be configured to form multiple cavities below the protective cover to reduce thermal stress on the protective cover. An encapsulant is disposed to cover the package substrate while leaving the top package surface exposed.

公开(公告)号：US20240186346A1

公开(公告)日：2024-06-06

申请号：US18516997

申请日：2023-11-22

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Jeffrey Punzalan ,  Catherine Cheh Yee Chang ,  Il Kwon Shim

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14683 ,  H01L24/32 ,  H01L27/14636 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227

Abstract: A semiconductor package for a sensor is disclosed. The package includes an opaque layer on the encapsulation to prevent the wire bonds encased by the encapsulation from being visible to the naked eye. This reduces or prevents reflectance which improves the performance of the sensor. In some cases, the opaque layer extends beyond the encapsulation to cover a peripheral portion of the cover to form a cover opaque region. The cover opaque region reduces or prevents flaring and scattering of light, further enhancing the performance of the sensor.