公开(公告)号：US20170148722A1

公开(公告)日：2017-05-25

申请号：US15428109

申请日：2017-02-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Chuen Khiang WANG ,  Nathapong SUTHIWONGSUNTHORN ,  Kriangsak SAE LE ,  Antonio B. DIMAANO, JR. ,  Catherine Bee Liang NG ,  Richard Te GAN ,  Kian Teng ENG

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49861 ,  H01L21/2885 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/4839 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

公开(公告)号：US20150380346A1

公开(公告)日：2015-12-31

申请号：US14849560

申请日：2015-09-09

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Chuen Khiang WANG ,  Nathapong SUTHIWONGSUNTHORN ,  Kriangsak SAE LE ,  Antonio Jr B DIMAANO ,  Catherine Bee Liang NG ,  Richard Te GAN ,  Kian Teng ENG

IPC: H01L23/495 ,  H01L21/56 ,  H01L25/065 ,  H01L21/288 ,  H01L23/48 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49861 ,  H01L21/2885 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/4839 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract translation: 公开了一种设备。 该装置包括具有第一和第二主表面的载体衬底。 第一表面包括管芯区域和接触焊盘，第二表面包括封装接触。 载体衬底包括图案化引线框架，其将导电迹线和具有通孔触点的通孔级限定在线路电平。 图案化引线框架提供接触焊盘和封装触点之间的互连。 载体衬底还包括隔离导电迹线和通孔触点的电介质层。 该装置包括安装在第一表面的管芯区域上的管芯。

公开(公告)号：US20180240726A1

公开(公告)日：2018-08-23

申请号：US15961839

申请日：2018-04-24

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong SUTHIWONGSUNTHORN ,  Antonio Jr. Bambalan DIMAANO ,  Rui HUANG ,  Hua Hong TAN ,  Kriangsak Sae LE ,  Beng Yeung HO ,  Nelson Agbisit DE VERA ,  Roel Adeva ROBLES ,  Wedanni Linsangan MICLA

IPC: H01L23/31 ,  H01L23/544 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

公开(公告)号：US20170294401A1

公开(公告)日：2017-10-12

申请号：US15477170

申请日：2017-04-03

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong SUTHIWONGSUNTHORN ,  John Ducyao BELERAN ,  Serafin Padilla PEDRON, JR.

IPC: H01L23/00 ,  B81B7/00 ,  H01L23/053

CPC classification number: H01L23/04 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/053 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/10158 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.

公开(公告)号：US20170117185A1

公开(公告)日：2017-04-27

申请号：US15402192

申请日：2017-01-09

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： William John NELSON ,  Nathapong SUTHIWONGSUNTHORN ,  Beng Yeung HO ,  Poh Leng Wilson ONG

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/308 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/268 ,  H01L23/544 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/14 ,  H01L2223/54453 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

公开(公告)号：US20160104626A1

公开(公告)日：2016-04-14

申请号：US14881181

申请日：2015-10-13

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： William John NELSON ,  Nathapong SUTHIWONGSUNTHORN ,  Beng Yeung HO ,  Poh Leng Wilson ONG

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/14 ,  H01L2223/54453 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

Abstract translation: 介绍了切割晶片的方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片在主要器件区域上由多个管芯制成并且通过晶片的第一主表面上的切割通道彼此间隔开。 在晶片的第一或第二主表面上提供膜。 薄膜至少覆盖对应于主要装置区域的区域。 该方法还包括使用该膜作为蚀刻掩模和等离子体通过晶片的暴露的半导体材料蚀刻晶片以形成间隙，以将晶片上的多个管芯分离成多个单独的管芯。

公开(公告)号：US20170077007A1

公开(公告)日：2017-03-16

申请号：US15361487

申请日：2016-11-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong SUTHIWONGSUNTHORN ,  Antonio Jr. Bambalan DIMAANO ,  Rui HUANG ,  Hua Hong TAN ,  Kriangsak Sae LE ,  Beng Yeung HO ,  Nelson Agbisit DE VERA ,  Roel Adeva ROBLES ,  Wedanni Linsangan MICLA

IPC: H01L23/31 ,  H01L23/544 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。

公开(公告)号：US20150357256A1

公开(公告)日：2015-12-10

申请号：US14731484

申请日：2015-06-05

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong SUTHIWONGSUNTHORN ,  Antonio Jr. Bambalan DIMAANO ,  Rui HUANG ,  Hua Hong TAN ,  Kriangsak Sae LE ,  Beng Yeung HO ,  Nelson Agbisit DE VERA ,  Roel Adeva ROBLES ,  Wedanni Linsangan MICLA

IPC: H01L23/31 ,  H01L21/3105 ,  H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。