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86 条记录 (耗时 0.027 秒)

    Dynamic memory circuit with automatic refresh function
    41.
    发明授权
    Dynamic memory circuit with automatic refresh function 失效
    动态内存电路具有自动刷新功能

    公开(公告)号：US06438055B1

    公开(公告)日：2002-08-20

    申请号：US09688941

    申请日：2000-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Yasurou Matsuzaki

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： The present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input, the refresh operation is performed at the earlier internal operation cycle. And a refresh command generation circuit which generates the refresh command at a refresh time is created in the memory circuit.

    摘要翻译： 本发明是在动态存储电路中，根据外部指令将第一和第二内部动作周期分配给一个外部动作周期，在第一内部动作中，存储器核心进行与读出命令对应的读取动作， 在第二内部操作周期响应刷新命令的刷新操作。 此外，存储器核心执行在第一内部操作周期响应刷新命令的刷新操作，并且在第二内部操作周期执行与写入命令相对应的写入操作。 优选的是，当没有输入读取或写入命令时，在较早的内部操作周期执行刷新操作。 并且在存储器电路中创建在刷新时间产生刷新命令的刷新命令产生电路。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    42.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06424199B1

    公开(公告)日：2002-07-23

    申请号：US09978022

    申请日：2001-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03K3013

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Self-timing control circuit
    44.
    发明授权
    Self-timing control circuit 有权
    自定时控制电路

    公开(公告)号：US06239635B1

    公开(公告)日：2001-05-29

    申请号：US09325555

    申请日：1999-06-04

    申请人： Yasurou Matsuzaki

    发明人： Yasurou Matsuzaki

    IPC分类号： H03L700

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/222 ,  H03K3/03 ,  H03K3/354 ,  H03K5/13 ,  H03K2005/00247 ,  H03L7/00

    摘要： A self-timing control circuit relating to the present invention comprises a clock cycle counting circuit for counting ocillation pulses during a period corresponding to a cycle of the master clock and generating a clock cycle count value. The count value for a period corresponding to the cycle of the master clock is calculated with this clock cycle counting circuit. The self-timing control circuit further comprises a control clock generating portion for generating the control clock, as timed by synchronizing with the master clock, starting a count of the oscillation pulses, and counting up to the clock cycle count value. As a result, the control clock generated is delayed from the master clock by the time taken to count to the measured count value. The timing of the control clock is delayed from the master clock by one cycle or an integer multiple thereof.

    摘要翻译： 涉及本发明的自定时控制电路包括时钟周期计数电路，用于在对应于主时钟的周期的周期内计数闭合脉冲并产生时钟周期计数值。 通过该时钟周期计数电路计算与主时钟的周期对应的期间的计数值。 自定时控制电路还包括控制时钟产生部分，用于通过与主时钟同步，启动振荡脉冲的计数并计数到时钟周期计数值来产生控制时钟。 结果，产生的控制时钟从主时钟延迟计数到测量的计数值所花费的时间。 控制时钟的定时从主时钟延迟一个周期或其整数倍。

    Semiconductor device having voltage generation circuit
    46.
    发明授权
    Semiconductor device having voltage generation circuit 失效
    具有电压产生电路的半导体装置

    公开(公告)号：US5929694A

    公开(公告)日：1999-07-27

    申请号：US933034

    申请日：1997-09-18

    申请人： Miki Yanagawa ,  Yasurou Matsuzaki

    发明人： Miki Yanagawa ,  Yasurou Matsuzaki

    IPC分类号： G11C11/413 ,  G05F3/20 ,  G11C5/14 ,  G11C8/08 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  G05F1/10

    CPC分类号： G11C5/143 ,  G05F3/205 ,  G11C5/145 ,  G11C8/08 ,  H02M3/073

    摘要： A semiconductor device operates in one of at least two different modes including a first mode and a second mode. The semiconductor device includes a first voltage generating circuit operating in the first mode and the second mode and having a power to supply a first amount of current in order to generate a predetermined voltage level, and a second voltage generating circuit operating only in the second mode and having a power to supply a second amount of current greater than the first amount of current in order to generate the predetermined voltage level, wherein the first voltage generating circuit increases the first amount of current in the second mode compared to in the first mode.

    摘要翻译： 半导体器件以包括第一模式和第二模式的至少两种不同模式中的一种工作。 半导体器件包括在第一模式和第二模式下工作的第一电压产生电路，并且具有供给第一电流量以产生预定电压电平的功率，以及仅在第二模式中工作的第二电压产生电路 并且具有提供大于第一电流量的第二量的电流以产生预定电压电平的电力的功率，其中与第一模式相比，第一电压产生电路增加第二模式中的第一电流量。

    Semiconductor device with circuitry for efficient information exchange
    48.
    发明授权
    Semiconductor device with circuitry for efficient information exchange 有权
    具有用于有效信息交换的电路的半导体器件

    公开(公告)号：US07782682B2

    公开(公告)日：2010-08-24

    申请号：US10006238

    申请日：2001-12-10

    申请人： Yasurou Matsuzaki ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Masao Taguchi

    IPC分类号： G11C7/77

    CPC分类号： H03M5/14 ,  G11C8/10 ,  H03M7/00 ,  H03M7/30

    摘要： A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

    摘要翻译： 具有寄存器和信息产生电路的半导体器件可以减少要传输的数据，从而节省电力。 寄存器存储第一个信息。 信息生成电路响应于从设备的外部获取的信号，生成指示第一信息的哪些位将被反转的第二信息。

    Semiconductor memory
    50.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US07317650B2

    公开(公告)日：2008-01-08

    申请号：US11715851

    申请日：2007-03-09

    申请人： Naoharu Shinozaki ,  Yasurou Matsuzaki

    发明人： Naoharu Shinozaki ,  Yasurou Matsuzaki

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40607 ,  G11C7/08 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

    摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

    摘要翻译： 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。