公开(公告)号：US20140159170A1

公开(公告)日：2014-06-12

申请号：US14183187

申请日：2014-02-18

Applicant: ASM IP Holding B.V.

Inventor： Petri Raisanen ,  Michael Givens ,  Mohith Verghese

IPC: H01L29/51 ,  H01L21/02

CPC classification number: H01L21/02233 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L22/12 ,  H01L22/20 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.

Abstract translation: 提供了与在衬底上形成膜堆叠的方法相关的实施例。 一个示例性方法包括将基底暴露于活化氧物质并将基底的暴露表面转化为第一介电材料的连续单层。 该示例性方法还包括在第一介电材料的连续单层上形成第二介电材料，而不将基板暴露于空气断裂。

公开(公告)号：US20230357924A1

公开(公告)日：2023-11-09

申请号：US18141125

申请日：2023-04-28

Applicant: ASM IP Holding B.V.

Inventor： Eric James Shero ,  Charles Dezelah ,  Ren-Jie Chang ,  Qi Xie ,  Perttu Sippola ,  Petri Raisanen

IPC: C23C16/40 ,  C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/768

CPC classification number: C23C16/405 ,  C23C16/045 ,  C23C16/4408 ,  C23C16/45553 ,  H01L21/02175 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/76831

Abstract: Vapor deposition methods and related systems are provided for depositing layers comprising vanadium and oxygen. In some embodiments, the methods comprise contacting a substrate in a reaction space with alternating pulses of a vapor-phase vanadium precursor and a vapor-phase oxygen reactant. The reaction space may be purged, for example, with an inert gas, between reactant pulses. The methods may be used to fill a gap on a substrate surface. Reaction conditions, including deposition temperature and reactant pulse and purge times may be selected to achieve advantageous gap fill properties. In some embodiments, the substrate on which deposition takes place is maintained at a relatively low temperature, for example between about 50° C. and about 185° C.

公开(公告)号：US20230175129A1

公开(公告)日：2023-06-08

申请号：US18072764

申请日：2022-12-01

Applicant: ASM IP Holding B.V.

Inventor： Jereld Lee Winkler ,  Petri Raisanen ,  Po-Yi Su

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/34 ,  C23C16/08

CPC classification number: C23C16/45534 ,  C23C16/4408 ,  C23C16/34 ,  C23C16/08

Abstract: Methods for depositing a thin film with improved film qualities on a hydrogen-terminated surface of a substrate are disclosed. The methods may comprise an atomic layer deposition (ALD) process comprising a plurality of deposition cycles comprising contacting the substrate with a first vapor phase metal halide or metalorganic reactant, contacting the substrate with the second vapor phase reactant, and contacting the substrate with a growth inhibitor. A growth inhibitor may be a non-consumable agent that is not incorporated into the deposited film during the deposition process and helps improve the properties of the deposited film. The growth inhibitor may comprise a vapor phase halide, such as HCl, or an organic molecule.

公开(公告)号：US20230017569A1

公开(公告)日：2023-01-19

申请号：US17947230

申请日：2022-09-19

Applicant: ASM IP Holding B.V.

Inventor： Petri Raisanen ,  David Marquardt ,  Thomas Aswad

IPC: C23C16/44 ,  C23C16/56 ,  C23C16/46 ,  C23C16/455 ,  C23C16/458

Abstract: A semiconductor processing apparatus is disclosed. The apparatus may include, a reaction chamber and a susceptor dispose in the reaction chamber configured for supporting a substrate thereon, the susceptor comprising a plurality of through-holes in an axial direction of the susceptor. The apparatus may also include, a plurality of lift pins, each of the lift pins being disposed within a respective through-hole, and at least one gas transmitting channel comprising one or more gas channel outlets, the one or more gas channel outlets being disposed proximate to the through-holes. Methods for processing a substrate within a reaction chamber are also disclosed.

公开(公告)号：US11501973B2

公开(公告)日：2022-11-15

申请号：US17097275

申请日：2020-11-13

Applicant: ASM IP Holding B.V.

Inventor： Petri Raisanen ,  Mark Olstad ,  Jose Alexandro Romero ,  Dong Li ,  Ward Johnson ,  Peijun Chen

IPC: H01L21/285 ,  H01L29/49 ,  C23C16/455 ,  C23C16/32 ,  H01L21/28 ,  H01L29/78

Abstract: A method of depositing a material film on a substrate within a reaction chamber by a cyclical deposition process is disclosed. The method may include: contacting the substrate with a first vapor phase reactant and purging the reaction chamber with a first main purge. The method also includes: contacting the substrate with a second vapor phase reactant by two or more micro pulsing processes, wherein each micro pulsing process comprises: contacting the substrate with a micro pulse of a second vapor phase reactant; and purging the reaction chamber with a micro purge, wherein each of the micro pulses of the second vapor phase reactant provides a substantially constant concentration of the second vapor phase reactant into the reaction chamber. The method may also include; purging the reaction chamber with a second main purge. Device structures including a material film deposited by the methods of the disclosure are also disclosed.

公开(公告)号：US20220285147A1

公开(公告)日：2022-09-08

申请号：US17685525

申请日：2022-03-03

Applicant: ASM IP Holding B.V.

Inventor： Lifu Chen ,  Qi Xie ,  Charles Dezelah ,  Petro Deminskyi ,  Giuseppe Alessio Verni ,  Petri Raisanen ,  Eric James Shero

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/52 ,  C23C16/08

Abstract: Disclosed are methods and systems for depositing layers comprising a titanium, aluminum, and carbon. The layers are formed onto a surface of a substrate. The deposition process comprises a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

公开(公告)号：US20210391440A1

公开(公告)日：2021-12-16

申请号：US17411306

申请日：2021-08-25

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/455 ,  H01L29/49 ,  C23C16/34

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

公开(公告)号：US11164955B2

公开(公告)日：2021-11-02

申请号：US16924595

申请日：2020-07-09

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/455 ,  H01L29/49 ,  C23C16/34

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

公开(公告)号：US20210327715A1

公开(公告)日：2021-10-21

申请号：US17227621

申请日：2021-04-12

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Eric James Shero ,  Charles Dezelah ,  Giuseppe Alessio Verni ,  Petri Raisanen

IPC: H01L21/28 ,  H01L29/49 ,  C23C16/34 ,  C23C16/455 ,  C23C16/52

Abstract: Methods and systems for depositing chromium nitride layers onto a surface of the substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a deposition process, depositing a chromium nitride layer onto a surface of the substrate. The deposition process can include providing a chromium precursor to the reaction chamber and separately providing a nitrogen reactant to the reaction chamber. The deposition process may be a thermal cyclical deposition process.

公开(公告)号：US10734497B2

公开(公告)日：2020-08-04

申请号：US16038024

申请日：2018-07-17

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/455 ,  H01L29/49 ,  C23C16/34

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.