公开(公告)号：US20060246656A1

公开(公告)日：2006-11-02

申请号：US11115391

申请日：2005-04-27

申请人： Stephan Kudelka ,  Guenther Aichmayr

发明人： Stephan Kudelka ,  Guenther Aichmayr

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867

摘要： The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact, particularly for use in a semiconductor memory cell. More specifically, the present invention relates to a manufacturing method for a trench capacitor having an isolation collar with a metal conductive fill in the collar region connected to a metal fill in the capacitor region.

摘要翻译： 本发明涉及一种具有隔离环的沟槽式电容器的制造方法，隔离环经由埋入式触点在单侧与衬底电连接，特别用于半导体存储单元。 更具体地说，本发明涉及一种用于沟槽电容器的制造方法，该沟槽电容器具有隔离套环，该隔离套环在与电容器区域中的金属填充物连接的套环区域中具有金属导电填料。

公开(公告)号：US20050158961A1

公开(公告)日：2005-07-21

申请号：US11053508

申请日：2005-02-08

申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 沟槽电容器的由表圈和存储板的顶表面形成的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

公开(公告)号：US20050032324A1

公开(公告)日：2005-02-10

申请号：US10886053

申请日：2004-07-08

申请人： Stephan Kudelka ,  Albrecht Kieslich ,  Kevin Pears

发明人： Stephan Kudelka ,  Albrecht Kieslich ,  Kevin Pears

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L21/76895 ,  H01L27/10867

摘要： A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.

摘要翻译： 一种用于制造沟槽结构的方法，特别是具有绝缘套环的沟槽电容器，其通过埋入触点电连接到一侧的衬底。 制造包括例如使用具有相应的掩模开口的硬掩模在衬底中提供沟槽; 提供至少部分沟槽填充; 在所得结构上提供衬垫; 将杂质离子倾斜地注入到衬垫上，以改变衬垫的注入部分区域的蚀刻性能; 通过第一蚀刻选择性地去除衬垫的注入部分区域，用于从衬垫的互补部分区域形成衬垫掩模，其部分地掩盖沟槽填充物的顶侧; 使用所述衬垫掩模通过第二蚀刻去除所述沟槽填充的一部分; 并更换去除的沟槽填充部分。

公开(公告)号：US06853025B2

公开(公告)日：2005-02-08

申请号：US10248801

申请日：2003-02-20

申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 由套环和储存板的顶表面形成的沟槽电容器的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

公开(公告)号：US06605860B1

公开(公告)日：2003-08-12

申请号：US09597442

申请日：2000-06-20

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Raj Jammy ,  Ulrike Gruening

IPC分类号： H01L2906

CPC分类号： H01L21/28202 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/2822 ,  H01L21/3144 ,  H01L21/31658 ,  H01L27/10864 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S257/905

摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.

摘要翻译： 一种在硅主体上形成基本上均匀的厚的热生长二氧化硅材料的方法，其独立于凸轮轴。 沟槽形成在硅体的表面中，这样的沟槽具有设置在不同结晶平面中的侧壁，这些平面中的一个是100晶体平面，另外一个这样的平面是“10”平面。 在侧壁上形成基本均匀的氮化硅层。 具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅 具有比<110>平面上的厚度大于超过<100>平面的厚度。 对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分 在氮化硅材料的下面部分上的<110>面上的二氧化硅。 选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。 然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

公开(公告)号：US06566273B2

公开(公告)日：2003-05-20

申请号：US09893157

申请日：2001-06-27

申请人： Stephan Kudelka

发明人： Stephan Kudelka

IPC分类号： H01L21302

CPC分类号： H01L27/1087 ,  H01L21/30608 ,  H01L21/308

摘要： Methods for expanding trenches are disclosed. A trench is formed in a substrate having side walls including at least two crystallographic planes. One crystallographic plane is etchable at a faster rate than a second crystallographic plane. A dielectric layer is selectively grown on surfaces of the crystallographic planes such that the dielectric layer includes a greater thickness on one of the crystallographic plane than on the other. The dielectric layer and the substrate are etched such that an etch rate inversion is achieved. That is, the second crystallographic plane is effectively etched at a faster rate than the first crystallographic plane.

摘要翻译： 公开了扩大沟槽的方法。 在具有包括至少两个结晶平面的侧壁的基板中形成沟槽。 一个结晶平面可以以比第二个结晶平面更快的速度进行刻蚀。 电介质层选择性地生长在结晶平面的表面上，使得电介质层在结晶平面之一上包括比另一层上更大的厚度。 蚀刻电介质层和衬底，使得实现蚀刻速率反转。 也就是说，以比第一结晶平面更快的速率有效地蚀刻第二结晶平面。

公开(公告)号：US06458647B1

公开(公告)日：2002-10-01

申请号：US09940761

申请日：2001-08-27

申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Irene McStay

发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Irene McStay

IPC分类号： H01L218242

CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L27/11507

摘要： A process for forming a sacrificial collar (116) on the top portion of a deep trench (114). A nitride layer (116) is deposited within the trench (114). A semiconductor layer (120) is deposited over the nitride layer (116). A top portion of the semiconductor layer (120) is doped to form doped semiconductor layer (124). Undoped portions (120) of the semiconductor layer are removed, and the doped semiconductor layer (124) is used to pattern the nitride layer (116), removing the lower portion of nitride layer (116) from within deep trenches (114) and leaving a sacrificial collar (116) at the top of the trenches (114).

摘要翻译： 一种用于在深沟槽（114）的顶部上形成牺牲套环（116）的工艺。 氮化物层（116）沉积在沟槽（114）内。 半导体层（120）沉积在氮化物层（116）上。 掺杂半导体层（120）的顶部以形成掺杂半导体层（124）。 去除半导体层的未掺杂部分（120），并且使用掺杂半导体层（124）对氮化物层（116）进行图案化，从深沟槽（114）中去除氮化物层（116）的下部并离开 在所述沟槽（114）的顶部处的牺牲套环（116）。

公开(公告)号：US06440872B1

公开(公告)日：2002-08-27

申请号：US09706468

申请日：2000-11-03

申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Stephan Kudelka

发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Stephan Kudelka

IPC分类号： H01L2100

CPC分类号： H01L27/10867 ,  H01L27/10876

摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.

摘要翻译： 形成混合存储器单元的过程，该混合存储单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

公开(公告)号：US06406970B1

公开(公告)日：2002-06-18

申请号：US09945007

申请日：2001-08-31

申请人： Stephan Kudelka ,  Helmut Horst Tews

发明人： Stephan Kudelka ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： A process for forming a buried strap for memory cells of a semiconductor device having reduced process complexity and improved thickness control of the top trench oxide (TTO) (26). A first oxide layer (16) is deposited over a substrate (11) having trenches formed therein. A first semiconductor material (18) is deposited within the trenches (14). A nitride layer (20) is formed over exposed semiconductor substrate (20) within trenches (14), and a second semiconductor layer (22) is deposited over the nitride layer (20). The top surfaces of the second semiconductor layer (22) are doped to form doped regions (24) and leave undoped second semiconductor layer (22) on the trench (14) sidewalls. The undoped second semiconductor layer (22) is removed from the trench (14) sidewalls, and the doped semiconductor layer (24) within the trench (14) is oxidized to form an oxide region (26), which forms a TTO, within the doped second semiconductor layer (24).

摘要翻译： 一种用于形成半导体器件的存储单元的掩埋带的工艺，其具有降低的工艺复杂性和改进顶部沟槽氧化物（TTO）（26）的厚度控制。 在其上形成有沟槽的衬底（11）上沉积第一氧化物层（16）。 第一半导体材料（18）沉积在沟槽（14）内。 氮化物层（20）形成在沟槽（14）内的暴露的半导体衬底（20）之上，并且第二半导体层（22）沉积在氮化物层（20）上。 第二半导体层（22）的顶表面被掺杂以形成掺杂区域（24）并且在沟槽（14）侧壁上留下未掺杂的第二半导体层（22）。 从沟槽（14）侧壁去除未掺杂的第二半导体层（22），并且在沟槽（14）内的掺杂半导体层（24）被氧化以形成一个形成TTO的氧化物区域（26） 掺杂的第二半导体层（24）。

公开(公告)号：US06261972B1

公开(公告)日：2001-07-17

申请号：US09706641

申请日：2000-11-06

申请人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

发明人： Helmut Horst Tews ,  Mary Weybright ,  Stephan Kudelka ,  Oleg Gluschenkov ,  Suri Hegde

IPC分类号： H01L2100

CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/823462 ,  H01L27/10873 ,  H01L29/518 ,  Y10S438/981

摘要： A process for forming dual gate oxides of improved oxide thickness uniformity for use in high performance DRAM systems or logic circuits, comprising: a) growing a sacrificial oxide layer on a substrate; b) implanting a dopant through the sacrificial oxide layer; c) implanting a first dosage of nitrogen ions in the absence of a photoresist to form a nitrided silicon layer; d) subjecting the substrate to a rapid thermal anneal for a sufficient time and at a sufficient temperature to allow nitrogen to diffuse to the silicon/oxide interface; e) masking the substrate with a photoresist to define the locations of the thin oxides of the dual gate oxide; f) implanting a second dosage of nitrogen ions through the photoresist; g) stripping the photoresist and the sacrificial oxide layers; and h) growing by oxidation gate oxide layers characterized by improved oxide thickness uniformity in the nitrogen ion implanted areas in the thin and thick oxides.

摘要翻译： 一种用于形成用于高性能DRAM系统或逻辑电路的改进的氧化物厚度均匀性的双栅极氧化物的方法，包括：a）在衬底上生长牺牲氧化物层; b）通过所述牺牲氧化物层注入掺杂剂; c） 不存在光致抗蚀剂的氮离子的第一剂量形成氮化硅层; d）对衬底进行快速热退火足够的时间和足够的温度以允许氮扩散到硅/氧化物界面; e）用光致抗蚀剂掩蔽衬底以限定双栅氧化物的薄氧化物的位置; f）通过光致抗蚀剂注入第二剂量的氮离子; g）剥离光致抗蚀剂和牺牲氧化物层; 和）通过氧化栅氧化层生长，其特征在于在薄和厚的氧化物中的氮离子注入区域中改善的氧化物厚度均匀性。