公开(公告)号：US5846332A

公开(公告)日：1998-12-08

申请号：US680724

申请日：1996-07-12

申请人： Jun Zhao ,  Ashok Sinha ,  Avi Tepman ,  Mei Chang ,  Lee Luo ,  Alex Schreiber ,  Talex Sajoto ,  Stefan Wolff ,  Charles Dornfest ,  Michal Danek

发明人： Jun Zhao ,  Ashok Sinha ,  Avi Tepman ,  Mei Chang ,  Lee Luo ,  Alex Schreiber ,  Talex Sajoto ,  Stefan Wolff ,  Charles Dornfest ,  Michal Danek

IPC分类号： C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/509 ,  C23C16/54 ,  H01J37/32 ,  H01L21/205 ,  H01L21/285 ,  C23C16/00

CPC分类号： C23C16/45508 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/4585 ,  C23C16/46 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/3244 ,  H01J37/32477 ,  H01J37/32834 ,  H01J2237/2001

摘要： A substrate processing chamber, particularly a chemical vapor deposition (CVD) chamber used both for thermal deposition of a conductive material and a subsequently performed plasma process. The invention reduces thermal deposition of the conductive material on peripheral portions of the pedestal supporting a wafer and in a pumping channel exhausting the chamber. A peripheral ring placed on the pedestal, preferably also used to center the wafer, is thermally isolated from the pedestal so that its temperature is kept substantially lower than that of the wafer. Despite its thermal isolation, the peripheral ring is electrically connected to the pedestal to prevent arcing. The pumping channel is lined with various elements, some of which are electrically floating and which are designed so that conductive material deposited on these elements do not deleteriously affect a plasma generated for processing the wafer.

摘要翻译： 衬底处理室，特别是用于导电材料的热沉积和随后执行的等离子体工艺的化学气相沉积（CVD）室。 本发明减少了导电材料在支撑晶片的基座周边部分和排出腔室的泵送通道中的热沉积。 放置在基座上的优选也用于使晶片居中的外围环与基座热隔离，使得其温度保持基本上低于晶片的温度。 尽管其热隔离，外围环电连接到基座以防止电弧。 泵浦通道衬有各种元件，其中一些元件是电浮动的，并且被设计成使得沉积在这些元件上的导电材料不会有害地影响用于处理晶片的等离子体。

公开(公告)号：US08975184B2

公开(公告)日：2015-03-10

申请号：US13560688

申请日：2012-07-27

申请人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

发明人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  C23C16/0245 ,  C23C16/045 ,  C23C16/18 ,  C23C16/45536 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862

摘要： Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.

摘要翻译： 提供了使用具有良好填充而不使用成核层的低电阻率钨层填充特征的方法。 在某些实施方案中，该方法涉及在高分压氢存在下化学气相沉积钨之前的任选处理方法。 根据各种实施方案，处理过程可以包括均热步骤或等离子体处理步骤。 所得到的钨层由于消除常规钨成核层而降低了先进钨技术中的总接触电阻。

公开(公告)号：US20120077342A1

公开(公告)日：2012-03-29

申请号：US13242160

申请日：2011-09-23

申请人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

发明人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

IPC分类号： H01L21/768

CPC分类号： H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

摘要翻译： 一种处理衬底的方法包括提供包括金属层，布置在金属层上的电介质层以及形成在电介质层中的通孔和沟槽中的至少一个的衬底; 在第一沉积周期期间使用化学气相沉积（CVD）沉积金属，其中所述第一沉积周期长于将所述金属沉积在所述金属层上所需的第一成核周期; 在第二成核延迟周期之前停止第一沉积周期，其中需要第二成核周期将金属沉积在电介质层上; 执行存入和停止N次，其中N是大于或等于1的整数; 并且在执行之后，在比第二成核延迟时段长的第二沉积时段期间使用CVD沉积金属。

公开(公告)号：US07732314B1

公开(公告)日：2010-06-08

申请号：US11714465

申请日：2007-03-05

申请人： Michal Danek ,  Robert Rozbicki

发明人： Michal Danek ,  Robert Rozbicki

IPC分类号： H01L21/20

CPC分类号： H01L21/76814 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865

摘要： Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

摘要翻译： 在集成电路上形成金属扩散阻挡层的方法包括至少四个操作。 第一个操作通过PVD，ALD或CVD沉积阻挡材料以提供一些最小的覆盖。 第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。 第三个操作通过PVD，ALD或CVD沉积阻挡材料，以提供一些最小的覆盖范围，特别是在非通孔的底部。 第四操作沉积金属导电层。 使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。 此外，描述了保护未经过过孔的底部的技术。

公开(公告)号：US06673716B1

公开(公告)日：2004-01-06

申请号：US10060725

申请日：2002-01-30

申请人： Gerard C. D'Couto ,  George Tkach ,  Michael Woitge ,  Michal Danek

发明人： Gerard C. D'Couto ,  George Tkach ,  Michael Woitge ,  Michal Danek

IPC分类号： H01L2122

CPC分类号： H01L21/76843 ,  C23C14/0641 ,  C23C14/185 ,  H01L21/2855 ,  H01L21/28568

摘要： A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with controlling the deposition temperatures by integrating cooling steps into the Ti/TiN deposition processes to modulate the via and contact resistance. The Ti and TiN layers are deposited within a single deposition chamber, without the use of a collimator or a shutter.

摘要翻译： 在具有高纵横比开口的通孔和沟槽内沉积包含Ti和TiN的薄膜的方法。 在中空阴极磁控管装置中，使用非氮化模式的Ti靶在集成电路基板上形成Ti和TiN层，结合通过将冷却步骤集成到Ti / TiN沉积工艺中来调节通孔 和接触电阻。 Ti和TiN层沉积在单个沉积室内，而不使用准直器或快门。

公开(公告)号：US06500742B1

公开(公告)日：2002-12-31

申请号：US09617515

申请日：2000-07-14

申请人： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

发明人： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

IPC分类号： H01L2144

CPC分类号： H01L21/76864 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01J2237/2001 ,  H01J2237/336 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

摘要： The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber. The rf signal means is coupled to the showerhead and the wafer support for providing a first rf signal to the showerhead and a second rf signal to the wafer support.

公开(公告)号：US06251758B1

公开(公告)日：2001-06-26

申请号：US08810221

申请日：1997-02-28

申请人： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

发明人： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

IPC分类号： H01L2128

CPC分类号： H01L21/76864 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01J2237/2001 ,  H01J2237/336 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

摘要： The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber. The rf signal means is coupled to the showerhead and the wafer support for providing a first rf signal to the showerhead and a second rf signal to the wafer support.

摘要翻译： 放置在处理室中的晶片上的膜的构造可以通过以下步骤进行。 在晶片上沉积一层材料。 接下来，将材料层退火。 一旦退火完成，材料可能被氧化。 或者，一旦退火完成，材料可能暴露于硅气体。 沉积，退火和氧化或硅气体暴露都可以在相同的室中进行，而不需要从腔室中移除晶片，直到完成所有三个步骤。 用于进行这种原位结构的半导体晶片处理室可以包括处理室，喷头，晶片支架和射频信号装置。 淋浴头将气体供应到处理室中，而晶片支撑件在处理室中支撑晶片。 rf信号装置耦合到喷头和晶片支架，用于向喷头提供第一rf信号，并将第二rf信号耦合到晶片支架。

公开(公告)号：US6129044A

公开(公告)日：2000-10-10

申请号：US409477

申请日：1999-10-06

申请人： Jun Zhao ,  Ashok Sinha ,  Avi Tepman ,  Mei Chang ,  Lee Luo ,  Alex Schreiber ,  Talex Sajoto ,  Stefan Wolff ,  Charles Dornfest ,  Michal Danek

发明人： Jun Zhao ,  Ashok Sinha ,  Avi Tepman ,  Mei Chang ,  Lee Luo ,  Alex Schreiber ,  Talex Sajoto ,  Stefan Wolff ,  Charles Dornfest ,  Michal Danek

IPC分类号： C23C16/44 ,  C23C16/46 ,  C23C16/52 ,  C23C16/56 ,  H01J37/32 ,  C23C16/00 ,  G06F19/00

CPC分类号： C23C16/4411 ,  C23C16/4412 ,  C23C16/46 ,  C23C16/52 ,  C23C16/56 ,  H01J37/3244 ,  H01J37/32834 ,  H01J2237/2001

摘要： The present invention provides an approach which provides an increase in the number of usable substrates with a film, such as titanium nitride, deposited thereon at a sufficient deposition rate and where the film meets uniformity and resistivity specifications as well as providing good step coverage. In accordance with an embodiment, the present invention provides an apparatus for substrate processing. The apparatus circulates a heat exchange medium through a passage in a chamber body of a vacuum chamber, and heats a heater pedestal having a surface for supporting the substrate to a heater temperature. The heat exchange medium has a heat exchange temperature of about 60.degree. C. or less. The the apparatus also flows a gas into the chamber at a flow rate to deposit a film on a substrate, where the flow rate provides an effective temperature of the substrate lower than the heater temperature and where the film meets uniformity and resistance specifications after deposition onto a number of substrates. This number is less than twenty-five, in some embodiments, and less than ten in other embodiments. The use of the present invention thus avoids the discarding of the initial hundreds of processed substrates not meeting specifications that is typically experienced with the prior art processes.

摘要翻译： 本发明提供了一种方法，其以足够的沉积速率在其上沉积有诸如氮化钛的膜，并且其中膜满足均匀性和电阻率规格以及提供良好的阶梯覆盖，提高了可用基板的数量的增加。 根据实施例，本发明提供了一种用于基板处理的装置。 该装置使热交换介质通过真空室的室主体中的通道循环，并将具有用于支撑基板的表面的加热器基座加热到加热器温度。 热交换介质的热交换温度为约60℃以下。 该设备还以流速将气体流入室中，以将膜沉积在基底上，其中流速提供了低于加热器温度的基底的有效温度，并且其中膜在沉积之后满足均匀性和电阻规格 一些基板。 在其他实施例中，该数量少于二十五个，在一些实施例中小于十个。 因此，本发明的使用避免了丢弃初始数百个处理过的基板，这些基板不符合现有技术工艺通常经历的规格。

公开(公告)号：US08778797B2

公开(公告)日：2014-07-15

申请号：US13242160

申请日：2011-09-23

申请人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

发明人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

IPC分类号： H01L21/44

CPC分类号： H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

摘要翻译： 一种处理衬底的方法包括提供包括金属层，布置在金属层上的电介质层以及形成在电介质层中的通路和沟槽中的至少一个的衬底; 在第一沉积周期期间使用化学气相沉积（CVD）沉积金属，其中所述第一沉积周期长于将所述金属沉积在所述金属层上所需的第一成核周期; 在第二成核延迟周期之前停止第一沉积周期，其中需要第二成核周期将金属沉积在电介质层上; 执行存入和停止N次，其中N是大于或等于1的整数; 并且在执行之后，在比第二成核延迟时段长的第二沉积时段期间使用CVD沉积金属。

公开(公告)号：US20110221044A1

公开(公告)日：2011-09-15

申请号：US12723532

申请日：2010-03-12

申请人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

发明人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.

摘要翻译： 公开了用于在铜插塞和硅之间具有插入钨层的铜填充硅通孔（TSV）的装置和方法。 方法对于具有或不具有TSV特征的镶嵌处理是有用的。 钨层用作扩散阻挡层，用于铜电解填料的种子层和减少铜和硅之间CTE引起的应力的手段。 描述了钨层对硅和铜层与钨的粘附。