公开(公告)号：US20120077342A1

公开(公告)日：2012-03-29

申请号：US13242160

申请日：2011-09-23

申请人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

发明人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

IPC分类号： H01L21/768

CPC分类号： H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

摘要翻译： 一种处理衬底的方法包括提供包括金属层，布置在金属层上的电介质层以及形成在电介质层中的通孔和沟槽中的至少一个的衬底; 在第一沉积周期期间使用化学气相沉积（CVD）沉积金属，其中所述第一沉积周期长于将所述金属沉积在所述金属层上所需的第一成核周期; 在第二成核延迟周期之前停止第一沉积周期，其中需要第二成核周期将金属沉积在电介质层上; 执行存入和停止N次，其中N是大于或等于1的整数; 并且在执行之后，在比第二成核延迟时段长的第二沉积时段期间使用CVD沉积金属。

公开(公告)号：US08778797B2

公开(公告)日：2014-07-15

申请号：US13242160

申请日：2011-09-23

申请人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

发明人： Juwen Gao ,  Rajkumar Jakkaraju ,  Michal Danek ,  Wei Lei

IPC分类号： H01L21/44

CPC分类号： H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

摘要翻译： 一种处理衬底的方法包括提供包括金属层，布置在金属层上的电介质层以及形成在电介质层中的通路和沟槽中的至少一个的衬底; 在第一沉积周期期间使用化学气相沉积（CVD）沉积金属，其中所述第一沉积周期长于将所述金属沉积在所述金属层上所需的第一成核周期; 在第二成核延迟周期之前停止第一沉积周期，其中需要第二成核周期将金属沉积在电介质层上; 执行存入和停止N次，其中N是大于或等于1的整数; 并且在执行之后，在比第二成核延迟时段长的第二沉积时段期间使用CVD沉积金属。

公开(公告)号：US08207062B2

公开(公告)日：2012-06-26

申请号：US12556490

申请日：2009-09-09

申请人： Juwen Gao ,  Wei Lei ,  Michal Danek ,  Erich Klawuhn ,  Sean Chang ,  Ron Powell

发明人： Juwen Gao ,  Wei Lei ,  Michal Danek ,  Erich Klawuhn ,  Sean Chang ,  Ron Powell

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  C23C16/0272 ,  C23C16/0281 ,  C23C16/06 ,  C23C16/14 ,  H01L21/28562 ,  H01L21/76856

摘要： Methods of improving the adhesion of low resistivity tungsten/tungsten nitride layers are provided. Low resistivity tungsten/tungsten nitride layers with good adhesion are formed by treating a tungsten or tungsten nitride layer before depositing low resistivity tungsten. Treatments include a plasma treatment and a temperature treatment. According to various embodiments, the treatment methods involve different gaseous atmospheres and plasma conditions.

摘要翻译： 提供了改善低电阻率钨/氮化钨层的附着力的方法。 通过在沉积低电阻率钨之前处理钨或氮化钨层来形成具有良好粘附性的低电阻率钨/氮化钨层。 处理包括等离子体处理和温度处理。 根据各种实施方案，处理方法涉及不同的气体气氛和等离子体条件。

公开(公告)号：US20110059608A1

公开(公告)日：2011-03-10

申请号：US12556490

申请日：2009-09-09

申请人： Juwen Gao ,  Wei Lei ,  Michal Danek ,  Erich Klawuhn ,  Sean Chang ,  Ron Powell

发明人： Juwen Gao ,  Wei Lei ,  Michal Danek ,  Erich Klawuhn ,  Sean Chang ,  Ron Powell

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C16/0272 ,  C23C16/0281 ,  C23C16/06 ,  C23C16/14 ,  H01L21/28562 ,  H01L21/76856

摘要： Methods of improving the adhesion of low resistivity tungsten/tungsten nitride layers are provided. Low resistivity tungsten/tungsten nitride layers with good adhesion are formed by treating a tungsten or tungsten nitride layer before depositing low resistivity tungsten. Treatments include a plasma treatment and a temperature treatment. According to various embodiments, the treatment methods involve different gaseous atmospheres and plasma conditions.

摘要翻译： 提供了改善低电阻率钨/氮化钨层的附着力的方法。 通过在沉积低电阻率钨之前处理钨或氮化钨层来形成具有良好粘附性的低电阻率钨/氮化钨层。 处理包括等离子体处理和温度处理。 根据各种实施方案，处理方法涉及不同的气体气氛和等离子体条件。

公开(公告)号：US20120080793A1

公开(公告)日：2012-04-05

申请号：US13251446

申请日：2011-10-03

申请人： Michal Danek ,  Juwen Gao ,  Ronald A. Powell ,  Aaron R. Fellis

发明人： Michal Danek ,  Juwen Gao ,  Ronald A. Powell ,  Aaron R. Fellis

IPC分类号： H01L23/48 ,  H01L21/28 ,  H01L21/768

CPC分类号： H01L21/76876 ,  H01L21/28562 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/53261 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.

摘要翻译： 某些实施例涉及由钨或其它导电材料的覆盖层的消减图案形成的局部互连。 钨或其他沉积金属的晶粒尺寸可以生长到相对较大的尺寸，这导致增加的导电性，这是由于例如当电子在传导期间从一个晶粒移动到下一个晶粒时在晶界处的电子散射减小。

公开(公告)号：US08709948B2

公开(公告)日：2014-04-29

申请号：US12723532

申请日：2010-03-12

申请人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

发明人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.

摘要翻译： 公开了用于在铜插塞和硅之间具有插入钨层的铜填充硅通孔（TSV）的装置和方法。 方法对于具有或不具有TSV特征的镶嵌处理是有用的。 钨层用作扩散阻挡层，用于铜电解填料的种子层和减少铜和硅之间CTE引起的应力的手段。 描述了钨层对硅和铜层与钨的粘附。

公开(公告)号：US20140030889A1

公开(公告)日：2014-01-30

申请号：US13560688

申请日：2012-07-27

申请人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

发明人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  C23C16/0245 ,  C23C16/045 ,  C23C16/18 ,  C23C16/45536 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862

摘要： Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.

摘要翻译： 提供了使用具有良好填充而不使用成核层的低电阻率钨层填充特征的方法。 在某些实施方案中，该方法涉及在高分压氢存在下化学气相沉积钨之前的任选处理方法。 根据各种实施方案，处理过程可以包括均热步骤或等离子体处理步骤。 所得到的钨层由于消除常规钨成核层而降低了先进钨技术中的总接触电阻。

公开(公告)号：US08975184B2

公开(公告)日：2015-03-10

申请号：US13560688

申请日：2012-07-27

申请人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

发明人： Feng Chen ,  Tsung-Han Yang ,  Juwen Gao ,  Michal Danek

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  C23C16/0245 ,  C23C16/045 ,  C23C16/18 ,  C23C16/45536 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862

摘要： Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.

摘要翻译： 提供了使用具有良好填充而不使用成核层的低电阻率钨层填充特征的方法。 在某些实施方案中，该方法涉及在高分压氢存在下化学气相沉积钨之前的任选处理方法。 根据各种实施方案，处理过程可以包括均热步骤或等离子体处理步骤。 所得到的钨层由于消除常规钨成核层而降低了先进钨技术中的总接触电阻。

公开(公告)号：US08617982B2

公开(公告)日：2013-12-31

申请号：US13251446

申请日：2011-10-03

申请人： Michal Danek ,  Juwen Gao ,  Ronald A. Powell ,  Aaron R. Fellis

发明人： Michal Danek ,  Juwen Gao ,  Ronald A. Powell ,  Aaron R. Fellis

IPC分类号： H01L21/4763

CPC分类号： H01L21/76876 ,  H01L21/28562 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/53261 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.

摘要翻译： 某些实施例涉及由钨或其它导电材料的覆盖层的消减图案形成的局部互连。 钨或其他沉积金属的晶粒尺寸可以生长到相对较大的尺寸，这导致增加的导电性，这是由于例如当电子在传导期间从一个晶粒移动到下一个晶粒时在晶界处的电子散射减小。

公开(公告)号：US20130302980A1

公开(公告)日：2013-11-14

申请号：US13851885

申请日：2013-03-27

申请人： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

发明人： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC分类号： H01L21/768

CPC分类号： H01L21/76879 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

摘要： Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).