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    METHOD OF ETCHING A THREE-DIMENSIONAL DIELECTRIC LAYER
    41.
    发明申请
    METHOD OF ETCHING A THREE-DIMENSIONAL DIELECTRIC LAYER 审中-公开

    公开(公告)号：US20190214266A1

    公开(公告)日：2019-07-11

    申请号：US16233948

    申请日：2018-12-27

    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

    Inventor： Nicolas POSSEME ,  Sebastien BARNOLA

    IPC: H01L21/311 ,  H01L29/66

    Abstract: A method for etching a dielectric layer covering at least one top and at least one flank of a semi-conductive material-based structure is provided, including a plurality of sequences, each including successive steps of: a first etching of the layer by plasma using a chemistry including at least a first fluorine-based compound and a second compound chosen from SiwCl(2w+2) and SiwF(2w+2), w, x, y, and z being whole numbers, and oxygen, the first etching: interrupting before complete consumption of the dielectric layer thickness on the flank and after complete consumption of the thickness on the top, and forming a first protective layer on the top and a second protective layer on the flank; and a second etching fully removing the second layer while conserving a portion of the first layer thickness, each sequence being repeated until complete removal of the dielectric layer on the flank.

    METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE
    45.
    发明申请
    METHOD FOR FORMING SPACERS FOR A TRANSISTOR GATE 有权
    用于形成晶体闸门的间隔物的方法

    公开(公告)号：US20160372568A1

    公开(公告)日：2016-12-22

    申请号：US15185446

    申请日：2016-06-17

    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME

    IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115

    CPC classification number: H01L29/6656 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

    Abstract: A method for forming spacers of a gate of a field-effect transistor is provided, the gate being located above a layer of a semiconductor material, the method including forming a dielectric layer covering the gate of the transistor; modifying the dielectric layer by putting the dielectric layer into presence with a plasma formed from a gas formed from at least one first non-carbonated gaseous component of which dissociation generates light ions and a second gaseous component comprising at least one species favoring dissociation of the first component in order to form the light ions, wherein a gas ratio between the first component and the second component is between 1:19 and 19:1.

    Abstract translation: 提供了一种用于形成场效应晶体管的栅极的间隔物的方法，所述栅极位于半导体材料层之上，所述方法包括形成覆盖晶体管的栅极的介电层; 通过将介电层置于由从解离产生轻离子的至少一种第一非碳酸化气体组分形成的气体形成的等离子体和包含至少一种有利于第一 组分以形成轻离子，其中第一组分和第二组分之间的气体比在1:19和19:1之间。

    METHOD FOR FORMING PATTERNS BY IMPLANTING
    46.
    发明申请
    METHOD FOR FORMING PATTERNS BY IMPLANTING 有权
    通过植入形成图案的方法

    公开(公告)号：US20160372325A1

    公开(公告)日：2016-12-22

    申请号：US15185540

    申请日：2016-06-17

    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME

    IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/265 ,  H01L21/3115

    CPC classification number: H01L21/0337 ,  H01L21/26533 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32135

    Abstract: A method of etching a layer including at least one pattern that has flanks is provided, including at least one step of modifying the layer by putting the layer in presence with a plasma into which CxHy is introduced and which includes ions heavier than hydrogen; and wherein the plasma creates a bombardment of ions with a hydrogen base coming from the CxHy, the bombardment being anisotropic according to a main direction of implantation parallel to the flanks and so as to modify portions of the layer that are inclined with respect to the main direction and so as to retain unmodified portions on the flanks, wherein chemical species of the plasma form a carbon film on the flanks; and at least one step of removing the modified layer to be etched using a selective etching of modified portions of the layer with respect to the carbon film.

    Abstract translation: 提供了一种蚀刻含有至少一个具有侧面的图案的层的方法，包括至少一个步骤，通过将层与存在于引入C x H y的等离子体并且包括比氢重的离子存在来修饰层; 并且其中所述等离子体产生具有来自C x H y的氢基团的离子的轰击，所述轰击根据平行于所述侧面的主要注入方向是各向异性的，并且修改所述层相对于所述主体倾斜的部分 方向并且保持在侧面上的未改性部分，其中等离子体的化学物质在侧面上形成碳膜; 以及至少一个步骤，通过相对于碳膜选择性地蚀刻该层的改性部分来去除待蚀刻的改质层。

    METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS
    47.
    发明申请
    METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS 审中-公开
    制造三维集成电路的方法

    公开(公告)号：US20160181155A1

    公开(公告)日：2016-06-23

    申请号：US14976958

    申请日：2015-12-21

    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

    Inventor： Fabien DEPRAT ,  Perrine BATUDE ,  Yves MORAND ,  Heimanu NIEBOJEWKSI ,  Nicolas POSSEME

    IPC: H01L21/768

    CPC classification number: H01L21/76831 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/8221 ,  H01L27/0688

    Abstract: Method of making an integrated circuit, comprising at least the following steps:a) form a first semiconducting or conducting element, covered with a first insulating layer on which there is a second semiconducting or conducting element, covered with a second insulating layer;b) form an opening passing through at least the second insulating layer, exposing a portion of the second element and opening up at least partly on the second element or adjacent to the second element;c) form a spacer located at the second element and comprising at least one dielectric material located at least between the second element and the opening;d) prolong the opening through the first insulating layer as far as the first element; ande) fill the opening with at least one conducting material, so as to form a contact.FIG 1G.

    Abstract translation: 制造集成电路的方法，至少包括以下步骤：a）形成第一半导体或导电元件，其被第一绝缘层覆盖，其上存在第二绝缘层，第二绝缘层被第二绝缘层覆盖; b）形成通过至少所述第二绝缘层的开口，暴露所述第二元件的一部分并且至少部分地在所述第二元件上或邻近所述第二元件开口; c）形成位于所述第二元件处的间隔件，并且包括至少一个位于所述第二元件和所述开口之间的电介质材料; d）延长穿过第一绝缘层的开口，直到第一元件; 和e）用至少一种导电材料填充开口，以形成接触。 图1G。

    METHOD FOR THE SURFACE ETCHING OF A THREE-DIMENSIONAL STRUCTURE
    48.
    发明申请
    METHOD FOR THE SURFACE ETCHING OF A THREE-DIMENSIONAL STRUCTURE 有权
    三维结构表面蚀刻的方法

    公开(公告)号：US20160079396A1

    公开(公告)日：2016-03-17

    申请号：US14855807

    申请日：2015-09-16

    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives

    Inventor： Nicolas POSSEME ,  Christian ARVET ,  Sebastien BARNOLA

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/311

    CPC classification number: H01L29/66795 ,  H01L21/2658 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/785

    Abstract: A method for etching a dielectric layer located on the surface of a three-dimensional structure formed on a face of a substrate oriented along a plane of a substrate, which includes a step of implanting ions so as to directionally create a top layer in the dielectric layer. Such top layer is thus not formed everywhere. Then, the layer in question is removed, except on the predefined zones, such as flanks of a transistor gate. A selective etching of the dielectric layer is executed relative to the material of the residual part of the top layer and relative to the material of the face of the substrate.

    Abstract translation: 一种用于蚀刻位于沿着衬底平面取向的衬底的表面上的三维结构的表面上的电介质层的方法，其包括注入离子以在电介质中定向地形成顶层的步骤 层。 因此，这样的顶层不会在任何地方形成。 然后，去除所讨论的层，除了预定义的区域，例如晶体管栅极的侧面。 相对于顶层的剩余部分的材料和相对于衬底的表面的材料的材料执行电介质层的选择性蚀刻。

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