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243 条记录 (耗时 0.037 秒)

    MOS Devices with Partial Stressor Channel
    42.
    发明申请
    MOS Devices with Partial Stressor Channel 有权
    具有部分应力通道的MOS器件

    公开(公告)号：US20090224337A1

    公开(公告)日：2009-09-10

    申请号：US12467847

    申请日：2009-05-18

    申请人： Ming-Hua Yu ,  Mong-Song Liang ,  Tze-Liang Lee ,  Jr-Hung Li

    发明人： Ming-Hua Yu ,  Mong-Song Liang ,  Tze-Liang Lee ,  Jr-Hung Li

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836 ,  Y10S438/938

    摘要： A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.

    摘要翻译： 半导体结构包括具有第一晶格常数的半导体衬底; 半导体衬底上的栅极电介质; 半导体衬底上的栅电极; 以及在半导体衬底中具有至少一部分并且与栅电极相邻的应力源。 应力源在与栅电极相邻的一侧具有倾斜的侧壁。 应激源包括具有与第一晶格常数基本不同的第二晶格常数的第一应力层; 以及第一应力层上的第二应力层，其中第二应力源具有与第一和第二晶格常数基本上不同的第三晶格常数。

    Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices
    43.
    发明申请
    Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices 审中-公开
    硅栅结构的多晶硅层，包括MOSFET栅电极和3D器件

    公开(公告)号：US20080093682A1

    公开(公告)日：2008-04-24

    申请号：US11583491

    申请日：2006-10-18

    申请人： Liang-Gi Yao ,  Jin Ying ,  Hun-Jan Tao ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Jin Ying ,  Hun-Jan Tao ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823443 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

    摘要： Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.

    摘要翻译： 提供了具有硅化物栅电极和制造方法的半导体结构。 一种器件包括形成在第一有源区中的第一硅化结构和形成在第二有源区中的第二硅化结构。 两个硅化物结构具有不同的金属浓度。 形成硅化器件的方法包括在第一和第二器件制造区域上形成多晶硅结构。 实施例包括用金属替代第一器件制造区上的多晶硅结构的第一部分，并用金属代替第二器件制造区上的多晶硅结构的第二部分。 优选地，第二部分不同于第一部分。 实施例还包括使第一和第二器件制造区上的多晶硅结构与金属反应以形成硅化物。

    Semiconductor device and fabrication method thereof
    45.
    发明申请
    Semiconductor device and fabrication method thereof 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20070152306A1

    公开(公告)日：2007-07-05

    申请号：US11324334

    申请日：2006-01-04

    申请人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

    发明人： Chien-Hsueh Shih ,  Shau-Lin Shue ,  Mong-Song Liang ,  Chao-Hsien Peng

    IPC分类号： H01L23/58 ,  H01L21/4763

    CPC分类号： H01L21/2885 ,  C23C18/1889 ,  C23C18/1893 ,  C25D5/54 ,  C25D13/04 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877

    摘要： A semiconductor device and fabrication method thereof. The semiconductor device comprises a substrate, an electroactive organic layer with conformal step coverage and uniform thickness, and a metal layer. The substrate is a conductive substrate or a nonconductive substrate with a conductive layer formed thereon. The electroactive organic layer and the metal layer are formed sequentially on the conductive substrate or the conductive layer, wherein the electroactive organic layer comprises metal atoms and serves as a seed layer, resulting in the metal layer formed in-situ.

    摘要翻译： 半导体器件及其制造方法。 半导体器件包括基底，具有适形阶梯覆盖和均匀厚度的电活性有机层和金属层。 衬底是其上形成有导电层的导电衬底或非导电衬底。 所述电活性有机层和所述金属层依次形成在所述导电性基板或所述导电层上，其中所述电活性有机层包含金属原子并且用作种子层，导致所述金属层原位形成。

    Method for producing low defect density strained -Si channel MOSFETS
    46.
    发明授权
    Method for producing low defect density strained -Si channel MOSFETS 有权
    低缺陷密度应变-Si沟道MOSFET的制造方法

    公开(公告)号：US07202142B2

    公开(公告)日：2007-04-10

    申请号：US10838721

    申请日：2004-05-03

    申请人： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/665 ,  H01L29/78

    摘要： A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.

    摘要翻译： 一种硅应变通道MOSFET器件及其形成方法，该方法提供提供晶片生产能力和低缺陷密度的方法，包括提供硅衬底的步骤; 使用选自乙硅烷，丙硅烷，二氯硅烷和硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 并且使用至少一种选自乙硅烷，丙硅烷，二氯硅烷和硅烷的沉积前体外延生长第二硅层。

    LOW K DIELECTRIC SURFACE DAMAGE CONTROL
    47.
    发明申请
    LOW K DIELECTRIC SURFACE DAMAGE CONTROL 有权
    低K电介质表面损伤控制

    公开(公告)号：US20070026668A1

    公开(公告)日：2007-02-01

    申请号：US11457888

    申请日：2006-07-17

    申请人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

    发明人： Hun-Jan Tao ,  Ryan Chen ,  Mong-Song Liang

    IPC分类号： H01L21/465

    CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76807

    摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

    摘要翻译： 公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面 底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

    Method for producing high throughput strained-Si channel MOSFETS
    50.
    发明授权
    Method for producing high throughput strained-Si channel MOSFETS 失效
    生产高通量应变Si沟道MOSFET的方法

    公开(公告)号：US06982208B2

    公开(公告)日：2006-01-03

    申请号：US10838625

    申请日：2004-05-03

    申请人： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Kuen-Chyr Lee ,  Liang-Gi Yao ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L21/30

    CPC分类号： H01L21/02505 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/7842

    摘要： A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

    摘要翻译： 一种用于形成具有改善的晶片生产量和低缺陷密度的应变硅层器件的方法，包括提供硅衬底; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 以及使用至少一种选自乙硅烷和硅烷的沉积前体外延生长第二硅层。