公开(公告)号：US07161204B2

公开(公告)日：2007-01-09

申请号：US11098112

申请日：2005-04-04

Applicant: Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

Inventor： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract translation: 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

公开(公告)号：US20060255365A1

公开(公告)日：2006-11-16

申请号：US11483913

申请日：2006-07-10

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L31/00

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

公开(公告)号：US20060220119A1

公开(公告)日：2006-10-05

申请号：US11423457

申请日：2006-06-12

Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L21/823425 ,  H01L21/76224 ,  H01L21/823412 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

公开(公告)号：US07112495B2

公开(公告)日：2006-09-26

申请号：US10729095

申请日：2003-12-05

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/76

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract translation: 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128。 应变通道晶体管132形成在第二有源区中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US20060177997A1

公开(公告)日：2006-08-10

申请号：US11377105

申请日：2006-03-16

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC: H01L21/20

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

Abstract translation: 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US07078742B2

公开(公告)日：2006-07-18

申请号：US10655255

申请日：2003-09-04

Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

IPC: H01L31/0312 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7848 ,  Y10S438/938

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

公开(公告)号：US20060009001A1

公开(公告)日：2006-01-12

申请号：US10864952

申请日：2004-06-10

Applicant: Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

Inventor： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract translation: 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

公开(公告)号：US20060008958A1

公开(公告)日：2006-01-12

申请号：US11227264

申请日：2005-09-15

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Hu

IPC: H01L21/337 ,  H01L21/20 ,  H01L21/36 ,  H01L31/20

CPC classification number: H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

Abstract: A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.

Abstract translation: CMOS集成电路包括具有带有P阱的NMOS区域和具有N阱的PMOS区域的衬底。 在NMOS和PMOS区之间形成浅沟槽隔离（STI）区，并且在所述P阱区和所述N阱区之上形成包含应变SiGe层的复合硅层。 复合硅层在STI区域断开。 然后在NMOS和PMOS区域中的复合层上形成栅电极。

公开(公告)号：US20060003522A1

公开(公告)日：2006-01-05

申请号：US10881372

申请日：2004-06-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L21/8242

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US06955952B2

公开(公告)日：2005-10-18

申请号：US10383709

申请日：2003-03-07

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

CPC classification number: H01L29/1054 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

Abstract translation: 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于双轴拉伸污染增强电子迁移率的硅层中。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。