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63 条记录 (耗时 0.023 秒)

    Semiconductor memory device
    41.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5517457A

    公开(公告)日：1996-05-14

    申请号：US360289

    申请日：1994-12-21

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Non-volatile semiconductor memory device
    42.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5453955A

    公开(公告)日：1995-09-26

    申请号：US255904

    申请日：1994-06-07

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

    IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/06 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C16/26

    摘要： A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.

    摘要翻译： 非挥发性半导体存储器件包括用于将位线设置在预定读取电位以执行数据读取操作的读取充电晶体管，并且在读取操作期间读取用于将未选择的位线设置为接地电位的放电晶体管。 这些晶体管由不同的控制信号控制，通过根据输入地址对每隔一个位线检测地址变化而获得，使得读出的放电晶体管保持导通，以将未选择的位线设置在地电位之前， 在数据读取操作期间。

    Electrically erasable programmable read-only memory with electric field decreasing controller
    43.
    发明授权
    Electrically erasable programmable read-only memory with electric field decreasing controller 失效
    电可擦除可编程只读存储器，具有电场降低控制器

    公开(公告)号：US5402373A

    公开(公告)日：1995-03-28

    申请号：US201036

    申请日：1994-02-24

    申请人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

    发明人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/0483

    摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

    摘要翻译： NAND单元型EEPROM具有位线，其各自与包括四个存储单元晶体管的串联阵列的NAND单元单元相关联。 每个晶体管是具有控制栅极和用于数据存储的浮动栅极的MOSFET。 存储单元晶体管分别在其控制栅极处连接到字线。 NAND单元单元的一端通过第一选择晶体管连接到相应的位线; 其另一端经由第二选择晶体管连接到源极电压。 存储单元晶体管和选择晶体管布置在形成在衬底中的阱区中。 在擦除模式中，位线电压，衬底电压和阱电压保持在高电压，而字线为零伏。 选择晶体管的栅极电位被保持在高电压，由此这些选择晶体管的内部电场被削弱以改善其绝缘击穿特性。

    MOS dynamic ram
    46.
    发明授权
    MOS dynamic ram 失效
    MOS动态RAM

    公开(公告)号：US4630088A

    公开(公告)日：1986-12-16

    申请号：US719450

    申请日：1985-04-03

    申请人： Mitsugi Ogura ,  Masaki Momodomi

    发明人： Mitsugi Ogura ,  Masaki Momodomi

    IPC分类号： H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/94 ,  G11C11/24 ,  H01L27/02 ,  H01L29/06

    CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/7827 ,  H01L29/945 ,  Y10S257/911 ,  Y10S257/92

    摘要： A MOS dynamic RAM consists of integrated memory cells each having a MOSFET and a MOS capacitor. The MOS dynamic RAM comprises a semiconductor substrate of a first conductivity type on which periodic projections and recesses are formed, a source region of a second conductivity type formed in the upper surface of each projection, a drain region of the second conductivity type formed in a bottom portion of each projection, a channel region of the first conductivity type sandwiched between the source and drain regions, a gate insulating film formed on a side wall of each projection between the source and drain regions, a gate electrode formed on the gate insulating film, a first insulating film formed on the source region, and a first electrode of the MOS capacitor formed on the first insulating film. The MOSFET is constituted by the source, drain and channel regions, the gate insulating film and the gate electrode. The MOS capacitor is constituted by the source region, the first insulating film and the first electrode, and the source region serves as the second electrode thereof. The gate electrodes serve as word lines, and the first electrodes of MOS capacitor serve as bit lines.

    摘要翻译： MOS动态RAM由具有MOSFET和MOS电容器的集成存储单元组成。 MOS动态RAM包括形成有周期性突起和凹部的第一导电类型的半导体衬底，形成在每个突起的上表面中的第二导电类型的源极区域，形成在第二导电类型的漏极区域 每个突起的底部，夹在源极和漏极区之间的第一导电类型的沟道区，形成在源极和漏极区之间的每个突起的侧壁上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极 形成在源极区上的第一绝缘膜和形成在第一绝缘膜上的MOS电容器的第一电极。 MOSFET由源极，漏极和沟道区域，栅极绝缘膜和栅极电极构成。 MOS电容器由源极区域，第一绝缘膜和第一电极构成，源极区域用作第二电极。 栅极用作字线，MOS电容器的第一电极用作位线。

    Nonvolatile semiconductor memory device
    47.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4630087A

    公开(公告)日：1986-12-16

    申请号：US613059

    申请日：1984-05-22

    申请人： Masaki Momodomi

    发明人： Masaki Momodomi

    IPC分类号： H01L27/112 ,  G11C16/02 ,  G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/10 ,  G11C16/14 ,  G11C16/32 ,  H01L29/78

    摘要： In a nonvolatile semiconductor memory device having a matrix of electrically erasable and programmable memory cells each of which has a floating gate, an erase gate, and two control gates, a relationship among the potentials selectively applied to the floating gate, the erase gate, and the two control gates is preset to decrease changes in the threshold level of the half-selected memory cells, thereby achieving high reliability. In the writing mode, a voltage of +25 V is applied to the selected row and column control lines, a first low voltage of 0 V is applied to the remaining row and column control lines, and a second low voltage of +5 V is applied to a source control line. In the erasing mode, a low voltage of 0 V is applied to the selected row and column control lines, a first high voltage of +25 V is applied to the remaining row and column control lines, and a second high voltage of +20 V is applied to the source control line.

    摘要翻译： 在具有电可擦除和可编程存储单元的矩阵的非易失性半导体存储器件中，每一个具有浮置栅极，擦除栅极和两个控制栅极，选择性地施加到浮置栅极，擦除栅极和 预设两个控制栅极以减小半选择存储单元的阈值电平的变化，从而实现高可靠性。 在写入模式下，对所选择的行和列控制线施加+25V的电压，对剩余的行和列控制线施加0V的第一低电压，+ 5V的第二低电压 应用于源控制线。 在擦除模式中，对所选择的行和列控制线施加0V的低电压，对剩余的行和列控制线施加+25V的第一高电压，并且将+ 20V的第二高电压 应用于源控制线。

    Electrically erasable programmable read-only memory with NAND cell structure
    50.
    再颁专利
    Electrically erasable programmable read-only memory with NAND cell structure 失效
    具有NAND单元结构的电可擦除可编程只读存储器

    公开(公告)号：USRE35838E

    公开(公告)日：1998-07-07

    申请号：US430271

    申请日：1995-04-28

    申请人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

    发明人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

    IPC分类号： G11C16/16 ,  G11C17/00

    CPC分类号： G11C16/16

    摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

    摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。 存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。 每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。 这些半导体层形成在形成于基板的表面区域的P型阱层中。 阱层用作表面击穿防止层。 在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。 在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。 当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极 的存储单元和阱层。 因此，只能选择所选单元格。