公开(公告)号：US20080171431A1

公开(公告)日：2008-07-17

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

公开(公告)号：US07312531B2

公开(公告)日：2007-12-25

申请号：US11261200

申请日：2005-10-28

申请人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

发明人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/53276 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

公开(公告)号：US20070264843A1

公开(公告)日：2007-11-15

申请号：US11430623

申请日：2006-05-09

申请人： Lih-Ping Li ,  Yung-Cheng Lu ,  Tien-I. Bao ,  Syun-Ming Jang ,  Ying-Tsung Chen

发明人： Lih-Ping Li ,  Yung-Cheng Lu ,  Tien-I. Bao ,  Syun-Ming Jang ,  Ying-Tsung Chen

IPC分类号： H01L21/31

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/76829

摘要： A method for manufacturing an integrated circuit is provided. In one example, the method includes forming a substantially nitrogen-free silicon carbide layer over a substrate using a methyl silicate gas.

摘要翻译： 提供一种用于制造集成电路的方法。 在一个实例中，该方法包括使用甲基硅酸盐气体在基底上形成基本上无氮的碳化硅层。

公开(公告)号：US07256124B2

公开(公告)日：2007-08-14

申请号：US11094011

申请日：2005-03-30

申请人： Keng-Chu Lin ,  Yi-Chi Liao ,  Hung-Chun Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

发明人： Keng-Chu Lin ,  Yi-Chi Liao ,  Hung-Chun Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76825

摘要： A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

摘要翻译： 一种制造半导体器件的方法。 首先提供在基板的顶表面上具有图案化导电层的半导体衬底。 然后形成介电层以覆盖基板。 此后，执行电子束照射程序以退火图案化导电层并降低图案化导电层的电阻。

公开(公告)号：US07220677B2

公开(公告)日：2007-05-22

申请号：US11106120

申请日：2005-04-13

申请人： Lin-Ping Li ,  Yung-Cheng Lu ,  Wen-Chih Chiou ,  Chih-Hsien Lin

发明人： Lin-Ping Li ,  Yung-Cheng Lu ,  Wen-Chih Chiou ,  Chih-Hsien Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L22/10 ,  G01R31/2831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.

摘要翻译： 一种用于形成多级半导体器件以在WAT测试之后消除导电互连突起的方法，所述方法包括形成第一金属化层; 进行晶圆验收测试（WAT）工艺; 然后在金属化层上进行化学机械抛光（CMP）。

公开(公告)号：US07217648B2

公开(公告)日：2007-05-15

申请号：US11020372

申请日：2004-12-22

申请人： Yung-Cheng Lu ,  Ying-Tsung Chen ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

发明人： Yung-Cheng Lu ,  Ying-Tsung Chen ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L2221/1047

摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.

摘要翻译： 提供一种制造具有多孔低k电介质层的半导体器件的方法。 优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。 在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。 在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。 半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。 优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。

公开(公告)号：US20060276027A1

公开(公告)日：2006-12-07

申请号：US11144742

申请日：2005-06-06

申请人： Yung-Cheng Lu ,  Ming-Hsing Tsai

发明人： Yung-Cheng Lu ,  Ming-Hsing Tsai

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.

公开(公告)号：US20060232941A1

公开(公告)日：2006-10-19

申请号：US11108920

申请日：2005-04-18

申请人： Chi-Wei Huang ,  Feng-Kuan Lee ,  Yung-Cheng Lu

发明人： Chi-Wei Huang ,  Feng-Kuan Lee ,  Yung-Cheng Lu

IPC分类号： H05K7/20

CPC分类号： H01L21/4882 ,  F28F1/32 ,  F28F2275/025 ,  H01L23/3672 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heat sink includes multiple heat dissipating fins securely connected to each other and each heat dissipating fin having a board, a through hole defined through the board, a receiving space formed on an attachment on a side face of the board to communicate with the through hole, an adhesive heat conductive agent received in the receiving space and a heat conductive tube extending through aligned through holes of the heat dissipating fins, the adhesive heat conductive agent is so arranged in the receiving space that the adhesive heat conductive agent covers an outer periphery of the heat conductive tube and fills a gap between the heat conductive tube and the heat dissipating fins, thus engagement between the heat conductive tube and the heat dissipating fins is secured after the adhesive heat conductive agent has cooled and hardened.

摘要翻译： 散热片包括彼此牢固地连接的多个散热翅片，每个具有板的散热片，通过该板限定的通孔，形成在板的侧面上的附件上的容纳空间，以与通孔 接收在接收空间中的粘合导热剂和延伸穿过散热片的孔的导热管，所述粘合导热剂布置在所述容纳空间中，所述粘合导热剂覆盖所述散热片的外周 导热管并填充导热管和散热片之间的间隙，因此在粘合导热剂冷却和硬化之后，确保导热管与散热翅片之间的接合。

公开(公告)号：US20060228856A1

公开(公告)日：2006-10-12

申请号：US11094011

申请日：2005-03-30

申请人： Keng-Chu Lin ,  Yi-Chi Liao ,  H. Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

发明人： Keng-Chu Lin ,  Yi-Chi Liao ,  H. Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

IPC分类号： H01L21/8242

CPC分类号： H01L21/76877 ,  H01L21/76825

摘要： A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

摘要翻译： 一种制造半导体器件的方法。 首先提供在基板的顶表面上具有图案化导电层的半导体衬底。 然后形成介电层以覆盖基板。 此后，执行电子束照射程序以退火图案化导电层并降低图案化导电层的电阻。

公开(公告)号：US07074727B2

公开(公告)日：2006-07-11

申请号：US10615628

申请日：2003-07-09

申请人： Peng-Fu Hsu ,  Jyu-Horng Shieh ,  Yung-Cheng Lu ,  Hun-Jan Tao ,  Yuan-Hung Chiu

发明人： Peng-Fu Hsu ,  Jyu-Horng Shieh ,  Yung-Cheng Lu ,  Hun-Jan Tao ,  Yuan-Hung Chiu

IPC分类号： C08G77/00 ,  H01L21/768

CPC分类号： C08G77/38

摘要： Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.

摘要翻译： 低k有机硅酸盐电介质材料可以暴露于一系列试剂，包括卤化试剂，烷基化试剂和终止试剂，以反转由以前的处理步骤引起的介电性质的退化。