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    Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method
    41.
    发明授权
    Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method 有权
    三维应变量子阱和三维应变表面通道的Ge约束法

    公开(公告)号：US07767560B2

    公开(公告)日：2010-08-03

    申请号：US11864963

    申请日：2007-09-29

    申请人： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

    发明人： Been-Yih Jin ,  Robert S. Chau ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC分类号： H01L21/36 ,  H01L21/20

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/7851

    摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    46.
    发明授权
    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
    非平面半导体器件部分或完全缠绕在栅极电极和制造方法

    公开(公告)号：US07456476B2

    公开(公告)日：2008-11-25

    申请号：US10607769

    申请日：2003-06-27

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

    Method of forming a metal oxide dielectric
    48.
    发明授权
    Method of forming a metal oxide dielectric 有权
    形成金属氧化物电介质的方法

    公开(公告)号：US07326656B2

    公开(公告)日：2008-02-05

    申请号：US11362453

    申请日：2006-02-24

    申请人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    发明人： Justin K. Brask ,  Brian S. Doyle ,  Jack Kavalleros ,  Mark Doczy ,  Uday Shah ,  Robert S. Chau

    IPC分类号： H01L21/31

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  Y10S438/926 ,  Y10S438/974

    摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。 在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。 然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。 栅电极包括直接与栅介电层相邻形成的金属膜。 然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

    Nonplanar device with stress incorporation layer and method of fabrication
    49.
    发明授权
    Nonplanar device with stress incorporation layer and method of fabrication 有权
    具有应力结合层的非平面器件及其制造方法

    公开(公告)号：US07241653B2

    公开(公告)日：2007-07-10

    申请号：US11173443

    申请日：2005-06-30

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

    摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

    摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。