公开(公告)号：US20130134838A1

公开(公告)日：2013-05-30

申请号：US13305293

申请日：2011-11-28

申请人： Changhan Hobie Yun ,  Chi Shun Lo ,  Chengjie Zuo ,  Jonghae Kim

发明人： Changhan Hobie Yun ,  Chi Shun Lo ,  Chengjie Zuo ,  Jonghae Kim

IPC分类号： H01L41/107 ,  H01L41/22

CPC分类号： H01L41/107 ,  H01L41/047 ,  H03H9/02228 ,  Y10T29/42

摘要： This disclosure provides implementations of electromechanical systems piezoelectric resonator transformers, devices, apparatus, systems, and related processes. In one aspect, a transformer includes a piezoelectric layer; a first conductive layer arranged over a first surface of the piezoelectric layer including a first set of electrodes and a second set of electrodes interdigitated with the first set. The transformer includes a second conductive layer arranged over a second surface including at least a third set of electrodes. In some implementations, the transformer includes a first port capable of receiving an input signal and to which the first set of electrodes are coupled, and a second port capable of being coupled to a load and of outputting an output signal, the second set of electrodes being coupled to the second port. Generally, a ratio of the number of electrodes of the second set to the first set characterizes a transformation ratio.

摘要翻译： 本公开提供了机电系统压电谐振器变压器，装置，装置，系统和相关过程的实现。 一方面，变压器包括压电层; 布置在压电层的第一表面上的第一导电层，包括第一组电极和与第一组交叉的第二组电极。 变压器包括布置在包括至少第三组电极的第二表面上的第二导电层。 在一些实施方式中，变压器包括能够接收输入信号并且第一组电极被耦合的第一端口和能够耦合到负载并输出输出信号的第二端口，第二组电极 耦合到第二端口。 通常，第二组的电极数与第一组的比例表示变换比。

公开(公告)号：US20130120951A1

公开(公告)日：2013-05-16

申请号：US13356717

申请日：2012-01-24

申请人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Sang-June Park ,  Chi Shun Lo ,  Mario F. Velez ,  Jonghae Kim

IPC分类号： H05K1/03 ,  H01L21/60 ,  H05K7/06 ,  H01L21/58

CPC分类号： H01L27/0688 ,  H01L2224/18

摘要： A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset.

摘要翻译： 芯片组包括玻璃板，石英或蓝宝石片，以及在第一基底层的第一面上具有至少一个第一电路层的第一晶片。 第一晶片连接到片材，使得至少一个第一电路层位于第一基片层和片之间。 具有在第二衬底层的第一侧上的至少一个第二电路层的第二晶片连接到第一衬底层，使得至少一个第二电路层位于第二衬底层和第一衬底层之间。 还有一种形成芯片组的方法。

公开(公告)号：US20130113076A1

公开(公告)日：2013-05-09

申请号：US13293075

申请日：2011-11-09

申请人： Changhan YUN ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

发明人： Changhan YUN ,  Chengjie Zuo ,  Chi Shun Lo ,  Jonghae Kim ,  Mario F. Velez

IPC分类号： H01L21/02 ,  H01L29/92

CPC分类号： H01L29/66174 ,  H01G4/1272 ,  H01G4/33 ,  H01L28/40 ,  H01L28/75

摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.

公开(公告)号：US20130076209A1

公开(公告)日：2013-03-28

申请号：US13241356

申请日：2011-09-23

申请人： Chengjie Zuo ,  Chi Shun Lo ,  Sanghoon Joo ,  Changhan Yun ,  Jonghae Kim

发明人： Chengjie Zuo ,  Chi Shun Lo ,  Sanghoon Joo ,  Changhan Yun ,  Jonghae Kim

IPC分类号： H01L41/107 ,  H01L41/04 ,  H01L41/047

CPC分类号： H03H9/02157 ,  H03H9/02062 ,  H03H9/56

摘要： A method and apparatus for a piezoelectric resonator having combined thickness and width vibrational modes are disclosed. A piezoelectric resonator may include a piezoelectric substrate and a first electrode coupled to a first surface of the piezoelectric substrate. The piezoelectric resonator may further include a second electrode coupled to a second surface of the piezoelectric substrate, where the first surface and the second surface are substantially parallel and define a thickness dimension of the piezoelectric substrate. Furthermore, the thickness dimension and the width dimension of the piezoelectric substrate are configured to produce a resonance from a coherent combination of a thickness vibrational mode and a width vibrational mode when an excitation signal is applied to the electrodes.

摘要翻译： 公开了一种具有组合的厚度和宽度振动模式的压电谐振器的方法和装置。 压电谐振器可以包括压电衬底和耦合到压电衬底的第一表面的第一电极。 压电谐振器还可以包括耦合到压电基板的第二表面的第二电极，其中第一表面和第二表面基本平行并且限定压电基板的厚度尺寸。 此外，压电基板的厚度尺寸和宽度尺寸被构造成当激励信号施加到电极时，从厚度振动模式和宽度振动模式的相干组合产生谐振。

公开(公告)号：US08384507B2

公开(公告)日：2013-02-26

申请号：US12791023

申请日：2010-06-01

申请人： Xia Li ,  Jonghae Kim ,  Chi Shun Lo

发明人： Xia Li ,  Jonghae Kim ,  Chi Shun Lo

IPC分类号： H01F5/00

CPC分类号： H05K1/165 ,  H01F21/08 ,  H01F41/041 ,  H01F2017/002 ,  H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/645 ,  H01L2924/0002 ,  H05K1/0251 ,  Y10T29/4902 ,  H01L2924/00

摘要： A through via inductor or transformer in a high-resistance substrate in an electronic package. In one embodiment, the package comprises a target inductor which includes a through-via formed in the substrate through which a signal passes and a tuner inductor which includes a through-via formed in the substrate such that the through-via has an independent signal passing therethrough. The direction of the signal passing through the tuner inductor can be independently controlled to adjust the total inductance of the target inductor. In another embodiment, a transformer can comprise a primary loop and a secondary loop, each of which includes a plurality of through-vias that are coupled to a plurality of conductive traces. The primary loop forms a first continuous conductive path and the secondary loop forms a second continuous conductive path. A signal passing through the primary loop can induce a signal in the secondary loop such that the induced signal is dependent on the transformer ratio.

摘要翻译： 电子封装中的高电阻基板中的通孔电感器或变压器。 在一个实施例中，封装包括目标电感器，其包括形成在基板中的通孔，信号通过该通孔，以及调谐器电感器，其包括形成在基板中的通孔，使得通孔具有独立的信号通过 通过。 可以独立地控制通过调谐器电感器的信号的方向来调节目标电感器的总电感。 在另一个实施例中，变压器可以包括主回路和次级回路，每个回路包括耦合到多个导电迹线的多个通孔。 主回路形成第一连续导电路径，次级环形成第二连续导电路径。 通过主回路的信号可以在次级回路中感应出信号，使感应信号取决于变压器的比例。

公开(公告)号：US20130021304A1

公开(公告)日：2013-01-24

申请号：US13186277

申请日：2011-07-19

申请人： Chengjie Zuo ,  Chi Shun Lo ,  Changhan Yun ,  Jonghae Kim

发明人： Chengjie Zuo ,  Chi Shun Lo ,  Changhan Yun ,  Jonghae Kim

IPC分类号： G06F3/038 ,  H01L41/047

CPC分类号： H03H9/173 ,  H03H9/02228

摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. A resonator structure generally includes a first conductive layer with an input electrode, an output electrode, and a ground electrode. The ground electrode is disposed between the input electrode and the output electrode. In some implementations, the second conductive layer includes an input electrode, an output electrode, and a ground electrode. In some other implementations, a second conductive layer includes a pair of ground electrodes and a signal electrode in the form of an input or output electrode disposed between the ground electrodes. A piezoelectric layer is disposed between the first conductive layer and the second conductive layer. Sub-resonators can be defined in different regions of the structure, such that the piezoelectric layer is capable of moving to produce an output signal having frequencies at a first resonant frequency and a second resonant frequency.

摘要翻译： 本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。 谐振器结构通常包括具有输入电极，输出电极和接地电极的第一导电层。 接地电极设置在输入电极和输出电极之间。 在一些实施方案中，第二导电层包括输入电极，输出电极和接地电极。 在一些其他实施方案中，第二导电层包括一对接地电极和设置在接地电极之间的输入或输出电极形式的信号电极。 压电层设置在第一导电层和第二导电层之间。 次谐振器可以在结构的不同区域中定义，使得压电层能够移动以产生具有第一谐振频率和第二谐振频率的频率的输出信号。

公开(公告)号：US08138563B2

公开(公告)日：2012-03-20

申请号：US12188243

申请日：2008-08-08

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

IPC分类号： H01L29/82

CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

摘要翻译： 提供了后端行（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。 一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。 多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。 至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。 多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。 多个元件的大小和尺寸设置在第一方向或第二方向上，以阻止特定波长的电磁干扰通过。

公开(公告)号：US20120054423A1

公开(公告)日：2012-03-01

申请号：US12872282

申请日：2010-08-31

申请人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

发明人： Feng Wang ,  Shiqun Gu ,  Jonghae Kim ,  Matthew Michael Nowak

IPC分类号： G06F12/02

CPC分类号： G06F13/1647 ,  G06F12/0607 ,  G06F13/1642 ,  G06F13/1657 ,  G06F2213/0064

摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

摘要翻译： 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。 因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。

公开(公告)号：US20120040509A1

公开(公告)日：2012-02-16

申请号：US13279570

申请日：2011-10-24

申请人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Matthew Nowak

发明人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Matthew Nowak

IPC分类号： H01L21/02

CPC分类号： H01L27/0617 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0688 ,  H01L28/10 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底的第一侧上制造有源层。 该方法还包括在半导体衬底的第二侧上制造金属层。 金属层包括嵌入金属层内的无源器件。 无源器件可以通过通孔电耦合到有源层。

公开(公告)号：US20110084765A1

公开(公告)日：2011-04-14

申请号：US12576033

申请日：2009-10-08

申请人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

发明人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC分类号： H03F3/16 ,  H01F5/00

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

摘要翻译： 公开了三维片上电感器，变压器和射频放大器。 射频放大器包括一对变压器和晶体管。 变压器包括至少两个电感耦合电感器。 电感器包括第一金属层的多个段，第二金属层的多个段，第一电感器输入端，第二电感器输入端和耦合第一金属层的多个段的多个穿通硅通孔 以及第二金属层的多个段，以在第一电感器输入端和第二电感器输入端之间形成连续的，不相交的路径。 电感器可以具有对称或不对称的几何形状。 第一金属层可以是芯片的后端部分中的金属层。 第二金属层可以位于芯片的再分布设计层中。