公开(公告)号：US20050145852A1

公开(公告)日：2005-07-07

申请号：US10995566

申请日：2004-11-24

Applicant: Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/80 ,  H01L21/337 ,  H01L29/24 ,  H01L29/808 ,  H01L29/15

CPC classification number: H01L29/8083 ,  H01L29/1608

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract translation: 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US20050006716A1

公开(公告)日：2005-01-13

申请号：US10776338

申请日：2004-02-12

Applicant: Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

Inventor： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC: H01L21/04 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/07 ,  H01L27/088 ,  H01L27/095 ,  H01L29/24 ,  H01L29/80 ,  H01L29/808 ,  H01L29/00

CPC classification number: H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

Abstract translation: 半导体器件包括：第一场效应晶体管，其包括源极和栅极，并设置在碳化硅衬底中; 以及包括漏极和栅极并设置在所述衬底中的第二场效应晶体管。 第二场效应晶体管的漏极连接到第一场效应晶体管的源极。 第二场效应晶体管的栅极连接到第一场效应晶体管的栅极。

公开(公告)号：US06693340B1

公开(公告)日：2004-02-17

申请号：US09870040

申请日：2001-05-30

Applicant: Gehan Anil Joseph Amaratunga ,  Ranick Kian Ming Ng ,  Florin Udrea

Inventor： Gehan Anil Joseph Amaratunga ,  Ranick Kian Ming Ng ,  Florin Udrea

IPC: H01L2358

CPC classification number: H01L29/0634 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/7824 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral semiconductor device has a semiconductor layer on an insulating layer on a semiconductor substrate. The semiconductor layer has a region of a first conduction type and a region of a second conduction type with a drift region therebetween. The drift region is provided by a region of the first conduction type and a region of the second conduction type. The first and second conduction type drift regions are so arranged that when a reverse voltage bias is applied across the first and second conduction type regions of the semiconductor layer, the second conduction type drift region has an excess of charge relative to the first conduction type drift region which varies substantially linearly from the end of the drift region towards the first conduction type region of the semiconductor layer to the end of the drift region towards the second conduction type region of the semiconductor layer.

Abstract translation: 横向半导体器件在半导体衬底上的绝缘层上具有半导体层。 半导体层具有第一导电类型的区域和具有漂移区域的第二导电类型的区域。 漂移区域由第一导电类型的区域和第二导电类型的区域提供。 第一和第二导电类型漂移区域被布置成使得当跨越半导体层的第一和第二导电类型区域施加反向电压偏压时，第二导电类型漂移区域相对于第一导电类型漂移具有过量的电荷 区域，其从漂移区域的端部朝向半导体层的第一导电类型区域到漂移区域的端部朝向半导体层的第二导电类型区域基本上线性地变化。

公开(公告)号：US06426520B1

公开(公告)日：2002-07-30

申请号：US09636111

申请日：2000-08-10

Applicant: Tatjana Traijkovic ,  Florin Udrea ,  Gehan Anil Joseph Amaratunga

Inventor： Tatjana Traijkovic ,  Florin Udrea ,  Gehan Anil Joseph Amaratunga

IPC: H01L2974

CPC classification number: H01L29/0619 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/402 ,  H01L29/7455 ,  H01L29/749 ,  H01L29/7811

Abstract: A semiconductor device comprises an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device. The edge portion comprises a substrate region (23, 24) of a first semiconductor type, and the voltage termination structure comprises first and second layers (21 and 22) formed within the substrate region. The first and second layers (21 and 22) define regions each of a second semiconductor type.

Abstract translation: 一种半导体器件包括具有电压终端结构的有源区，位于器件的边缘部分附近与有源区相邻。 边缘部分包括第一半导体类型的衬底区域（23,24），并且电压终端结构包括形成在衬底区域内的第一和第二层（21和22）。 第一和第二层（21和22）限定每个第二半导体类型的区域。

公开(公告)号：US6111280A

公开(公告)日：2000-08-29

申请号：US341794

申请日：1999-09-14

Applicant: Julian Gardner ,  Florin Udrea

Inventor： Julian Gardner ,  Florin Udrea

IPC: G01N27/12 ,  G01N27/414 ,  G01N33/00 ,  H01L29/72

CPC classification number: G01N27/128

Abstract: A gas-sensing semiconductor device 1 is fabricated on a silicon substrate 2 having a thin silicon oxide insulating layer 3 on one side and a thin silicon layer 4 on top of the insulating layer 3 using CMOS SOI technology. The silicon layer 4 may be in the form of an island surrounded by a silicon oxide insulating barrier layer 4 formed by the known LOCOS oxidation technique, although other lateral isolation techniques may also be used. The device 1 includes at least one sensing area provided with a gas-sensitive layer 18, a MOSFET heater 6 for heating the gas-sensitive layer 18 to promote gas reaction with the gas-sensitive layer 18 and a sensor 16, which may be in the form of a chemoresistor, for providing an electrical output indicative of gas reaction with the gas-sensitive layer 18. As one of the final fabrication steps, the substrate 2 is back-etched so as to form a thin membrane 20 in the sensing area. Such a device can be produced at low cost using conventional CMOS SOI technology.

Abstract translation: PCT No.PCT / GB98 / 00100 Sec。 371 1999年9月14日第 102（e）1999年9月14日PCT PCT 1998年1月13日PCT公布。 公开号WO98 / 32009 日期1998年7月23日气体感测半导体器件1使用CMOS SOI技术在绝缘层3的一侧具有薄氧化硅绝缘层3和薄硅层4的硅衬底2上制造。 硅层4可以是由已知的LOCOS氧化技术形成的氧化硅绝缘阻挡层4所包围的岛的形式，尽管也可以使用其它横向隔离技术。 装置1包括设置有气体敏感层18的至少一个感测区域，用于加热气敏层18以促进与气体敏感层18的气体反应的MOSFET加热器6和传感器16，传感器16可处于 化学电阻器的形式，用于提供指示与气体敏感层18的气体反应的电输出。作为最终制造步骤之一，背衬蚀刻基板2，以便在感测区域中形成薄膜20 。 可以使用常规CMOS SOI技术以低成本制造这种器件。

公开(公告)号：US6091107A

公开(公告)日：2000-07-18

申请号：US9230

申请日：1998-01-20

Applicant: Gehan A. J. Amaratunga ,  Florin Udrea

Inventor： Gehan A. J. Amaratunga ,  Florin Udrea

IPC: H01L29/74 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/7396 ,  H01L29/7397

Abstract: An Insulated Gate Bipolar Transistor has a gate in the form of a trench positioned in a p region in a silicon body. The device operates in a thyristor mode having a virtual emitter which is formed during operation by the generation of an inversion layer at the bottom of the trench within the p region. The device is inherently safe and turns off rapidly as removal of a gate signal collapses the emitter. As the trench gate is situated within the p region, it can withstand high voltages when turned off as the reverse electric field is prevented from reaching the trench gate.

Abstract translation: 绝缘栅双极晶体管具有位于硅体中的p区域中的沟槽形式的栅极。 器件工作在具有虚拟发射极的晶闸管模式中，该虚拟发射极在工作期间通过在p区内的沟槽的底部产生反转层而形成。 该器件本质上是安全的，并且随着栅极信号的去除使发射极收缩而迅速关闭。 当沟槽栅极位于p区内时，当反向电场防止到达沟槽栅极时，它可以承受高电压。

公开(公告)号：US09080907B2

公开(公告)日：2015-07-14

申请号：US12739520

申请日：2008-10-24

Applicant: Ibraheem Haneef ,  Howard P. Hodson ,  Robert Miller ,  Florin Udrea

Inventor： Ibraheem Haneef ,  Howard P. Hodson ,  Robert Miller ,  Florin Udrea

IPC: G01F1/68 ,  G01F1/684 ,  G01F1/708 ,  G01N3/24

CPC classification number: G01F1/6845 ,  G01F1/7084 ,  G01N3/24 ,  G01N2203/0226 ,  G01N2203/0623

Abstract: This invention relates to hot film shear stress sensors and their fabrication. We describe a hot film shear stress sensor comprising a silicon substrate supporting a membrane having a cavity underneath, said membrane bearing a film of metal and having electrical contacts for heating said film, and wherein said membrane comprises a silicon oxide membrane, where in said metal comprises aluminium or tungsten, and wherein said membrane has a protective layer of a silicon-based material over said film of metal. In preferred embodiments the sensor is fabricated by a CMOS process and the metal comprises aluminium or tungsten.

Abstract translation: 本发明涉及热膜剪切应力传感器及其制造。 我们描述了一种热膜剪切应力传感器，其包括支撑具有下面空腔的膜的硅衬底，所述膜承载金属膜并具有用于加热所述膜的电触点，并且其中所述膜包括氧化硅膜，其中在所述金属 包括铝或钨，并且其中所述膜在所述金属膜上具有硅基材料的保护层。 在优选实施例中，传感器通过CMOS工艺制造，并且金属包括铝或钨。

公开(公告)号：US08853770B2

公开(公告)日：2014-10-07

申请号：US12724771

申请日：2010-03-16

Applicant: Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

Inventor： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

IPC: H01L29/76 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/407 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward the edge of the semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate and a second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover a portion of the termination structure oxide layer.

Abstract translation: 为功率晶体管提供终端结构。 端接结构包括具有有源区和端接区的半导体衬底。 衬底具有第一类导电性。 终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。 具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 在与边界相邻的侧壁上形成MOS栅极。 掺杂区域从与栅极间隔开的部分MOS栅极向半导体衬底的边缘延伸。 端接结构氧化物层形成在覆盖MOS栅极的一部分并朝向衬底边缘延伸的端接沟槽上。 第一导电层形成在半导体衬底的背侧表面上，并且第二导电层形成在有源区顶部，MOS栅极的暴露部分之上，并延伸以覆盖端接结构氧化物层的一部分。

公开(公告)号：US08716794B2

公开(公告)日：2014-05-06

申请号：US13131779

申请日：2010-08-10

Applicant: Xiaorong Luo ,  Florin Udrea

Inventor： Xiaorong Luo ,  Florin Udrea

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

Abstract translation: 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。

公开(公告)号：US08564097B2

公开(公告)日：2013-10-22

申请号：US12760754

申请日：2010-04-15

Applicant: Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

Inventor： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC: H01L27/082

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

Abstract translation: 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。