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57 条记录 (耗时 0.034 秒)

    Alumina ceramic composition
    41.
    发明授权
    Alumina ceramic composition 失效
    氧化铝陶瓷组合物

    公开(公告)号：US4668646A

    公开(公告)日：1987-05-26

    申请号：US900512

    申请日：1986-08-26

    申请人： Minato Ando ,  Masaaki Ito ,  Fumio Mizuno

    发明人： Minato Ando ,  Masaaki Ito ,  Fumio Mizuno

    IPC分类号： C04B35/111 ,  H01B3/12 ,  H01P7/10 ,  C04B35/10 ,  C04B35/46

    CPC分类号： C04B35/111

    摘要： An alumina ceramic composition to provide a low dielectric loss in the high frequency region upon sintering, which consists essentially of: 100 parts by weight of a base composition containing therein Al.sub.2 O.sub.3, CaO and TiO.sub.2 within their respective compositional range; and 0.03 to 3 parts by weight of La.sub.2 O.sub.3. The base composition is within a range A-B-C-D-E-A in the ternary diagram (Figure) in molar fraction:______________________________________ Al.sub.2 O.sub.3 CaO TiO.sub.2 ______________________________________ A 99.0 0.5 0.5 B 94.5 3.7 1.8 C 90.0 7.0 3.0 D 90.0 2.0 8.0 E 94.5 1.3 4.2 ______________________________________

    摘要翻译： 一种氧化铝陶瓷组合物，其在烧结时在高频区域提供低介电损耗，其基本上由以下组成：100重量份在其各自的组成范围内含有Al 2 O 3，CaO和TiO 2的基础组合物; 和0.03〜3重量份的La 2 O 3。 基础组成在摩尔分数三元图（图）中的A-B-C-D-E-A范围内：-Al 2 O 3 CaO TiO 2 -A 99.0 0.5 0.5 -B 94.5 3.7 1.8 -C 90.0 7.0 3.0 -D 90.0 2.0 8.0 -E 94.5 1.3 4.2 -

    Dielectric ceramic composition for high frequency purposes
    42.
    发明授权
    Dielectric ceramic composition for high frequency purposes 失效
    介电陶瓷组合物用于高频目的

    公开(公告)号：US4585745A

    公开(公告)日：1986-04-29

    申请号：US681947

    申请日：1984-12-14

    申请人： Tutomu Tunooka ,  Fumio Mizuno

    发明人： Tutomu Tunooka ,  Fumio Mizuno

    IPC分类号： H01B3/12 ,  C04B35/495 ,  H01P7/10 ,  C04B35/00

    CPC分类号： C04B35/495

    摘要： A dielectric ceramic composition, which has a high dielectric constant, low loss and stable temperature characteristics suited for the microwave frequency range, is obtained by the present invention. The dielectric ceramic composition according to the present invention is expressed as (Ba.sub.x Sr.sub.1-x)(Ni.sub.1/3 Nb.sub.2/3)O.sub.3 and with a mole fraction range of 0.ltoreq.x

    摘要翻译： 通过本发明获得具有适合于微波频率范围的高介电常数，低损耗和稳定的温度特性的介电陶瓷组合物。 根据本发明的电介质陶瓷组合物表示为（BaxSr1-x）（Ni1 / 3Nb2 / 3）O3，摩尔分数范围为0

    Memory array with larger memory capacitors at row ends
    43.
    发明授权
    Memory array with larger memory capacitors at row ends 失效
    存储阵列在行末端具有较大的存储电容

    公开(公告)号：US4118794A

    公开(公告)日：1978-10-03

    申请号：US851691

    申请日：1977-11-15

    申请人： Fumio Mizuno ,  Masamichi Ishihara

    发明人： Fumio Mizuno ,  Masamichi Ishihara

    IPC分类号： G11C11/404 ,  G11C11/4097 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

    CPC分类号： H01L27/10805 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/105

    摘要： A memory cell of a dynamic storage device is composed of a MOSFET and a capacitor. On a single semiconductor substrate, a plurality of such memory cells are regularly arranged so as to form a plurality of columns, with the result that they constitute a memory cell array or a memory cell mat. The capacitor for the memory cell is made up of a semiconductor region of the type which possesses a conductivity opposite to that of the semiconductor substrate, and a conductor film which is formed of polycrystalline silicon or the like on the semiconductor region through a comparatively thin insulating film. The areas of the capacitors in the memory cell column situated at an end portion of the memory cell mat are made larger than those of the capacitors of the memory cells at an inner or central portion of the memory cell mat. The memory cells at the end portion of the memory cell mat come to have information holding times equivalent to those of the memory cells at the central portion of the memory cell mat.

    摘要翻译： 动态存储装置的存储单元由MOSFET和电容器组成。 在单个半导体衬底上，多个这样的存储单元被规则地排列以形成多个列，结果它们构成存储单元阵列或存储单元垫。 用于存储单元的电容器由具有与半导体衬底的导电性相反的导电性的半导体区域和由半导体区域上的多晶硅等形成的导体膜构成，该导体膜通过较薄的绝缘 电影。 位于存储单元垫的端部的存储单元列中的电容器的面积比在存储单元垫的内部或中央部分的存储单元的电容器的面积大。 存储单元垫的端部处的存储单元具有与存储单元垫的中央部分的存储单元相同的信息保持时间。

    High-speed semiconductor device and method for manufacturing the same
    44.
    发明授权
    High-speed semiconductor device and method for manufacturing the same 失效
    高速半导体器件及其制造方法

    公开(公告)号：US08217466B2

    公开(公告)日：2012-07-10

    申请号：US11990491

    申请日：2006-08-01

    申请人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

    发明人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

    IPC分类号： H01L21/70

    CPC分类号： H01L27/1211 ,  H01L21/823493 ,  H01L27/0705 ,  H01L29/66795 ,  H01L29/785

    摘要： Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

    摘要翻译： 公开了一种半导体器件，其中晶体管的开关速度增加。 具体公开了一种半导体器件，包括形成在绝缘层的一部分上的半导体层，形成在半导体层的侧面上的第一晶体管，并具有第一栅极绝缘膜，第一栅电极和两个第一杂质层， 源极和漏极，以及形成在所述半导体层的另一个侧面上并具有第二栅极绝缘膜，第二栅极电极和形成源极和漏极的两个第二杂质层的第二晶体管。

    Semiconductor Device and Manufacturing Method Thereof
    46.
    发明申请
    Semiconductor Device and Manufacturing Method Thereof 失效
    半导体器件及其制造方法

    公开(公告)号：US20090096029A1

    公开(公告)日：2009-04-16

    申请号：US11990491

    申请日：2006-08-01

    申请人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

    发明人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L27/1211 ,  H01L21/823493 ,  H01L27/0705 ,  H01L29/66795 ,  H01L29/785

    摘要： Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

    摘要翻译： 公开了一种半导体器件，其中晶体管的开关速度增加。 具体公开了一种半导体器件，包括形成在绝缘层的一部分上的半导体层，形成在半导体层的侧面上的第一晶体管，并具有第一栅极绝缘膜，第一栅电极和两个第一杂质层， 源极和漏极，以及形成在所述半导体层的另一个侧面上并具有第二栅极绝缘膜，第二栅极电极和形成源极和漏极的两个第二杂质层的第二晶体管。

    Microstructured pattern inspection method
    47.
    发明申请
    Microstructured pattern inspection method 有权
    微结构图案检验方法

    公开(公告)号：US20070290697A1

    公开(公告)日：2007-12-20

    申请号：US11798395

    申请日：2007-05-14

    申请人： Fumihiro Sasajima ,  Osamu Komuro ,  Fumio Mizuno

    发明人： Fumihiro Sasajima ,  Osamu Komuro ,  Fumio Mizuno

    IPC分类号： G01N23/00

    CPC分类号： G03F7/70608 ,  G01N23/225 ,  G06T7/0004 ,  H01J37/265 ,  H01J37/28 ,  H01J2237/221 ,  H01J2237/24592 ,  H01J2237/2487

    摘要： The edges of the reticle are detected with respect to the microstructured patterns exposed by the stepper, and the shapes of the microstructured patterns at the surface and at the bottom of the photoresist are detected. The microstructured patterns are evaluated by calculating, and displaying on the screen, the dislocation vector that represents the relationship in position between the detected patterns on the surface and at the bottom of the photoresist. Furthermore, dislocation vectors between the microstructured patterns at multiple positions in a single-chip or single-shot area or on one wafer are likewise calculated, then the sizes and distribution status of the dislocation vectors at each such position are categorized as characteristic quantities, and the corresponding tendencies are analyzed. Thus, stepper or wafer abnormality is detected.

    摘要翻译： 相对于由步进器暴露的微结构化图案检测掩模版的边缘，并且检测光致抗蚀剂表面和底部处的微结构图案的形状。 通过在屏幕上计算和显示代表光刻胶表面和底部上检测到的图案之间的位置关系的位错矢量来评估微结构化图案。 此外，同样计算单芯片或单次照射区域或一个晶片上的多个位置处的微结构化图案之间的位错矢量，则将每个这样的位置处的位错矢量的尺寸和分布状态分类为特征量，并且 分析相应的趋势。 因此，检测到步进器或晶片异常。