公开(公告)号：US10276659B2

公开(公告)日：2019-04-30

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

公开(公告)号：US20180308930A1

公开(公告)日：2018-10-25

申请号：US15992431

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor device includes a vertically-oriented channel semiconductor (VOCS) structure positioned above a substrate and a first bottom spacer positioned above the substrate adjacent the VOCS structure. The first bottom spacer extends around less than an entirety of a perimeter of the VOCS structure. A gate structure is positioned around the VOCS structure. Only a portion of the gate structure is positioned vertically above the first bottom spacer so as to thereby define an air gap that is positioned under the gate structure. The air gap extends around a majority of a perimeter of the VOCS structure and a second bottom spacer positioned above the substrate. An upper portion of the second bottom spacer contacts a material formed around the VOCS structure so as to seal the air gap. The second bottom spacer has a vertical thickness that is greater than a vertical thickness of the air gap.

公开(公告)号：US10037919B1

公开(公告)日：2018-07-31

申请号：US15609603

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.

公开(公告)号：US10014370B1

公开(公告)日：2018-07-03

申请号：US15491420

申请日：2017-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel semiconductor (VOCS) structure and forming a gate structure around the VOCS structure and above the initial bottom spacer. In this example, the method also includes performing at least one etching process to remove at least a portion of the initial bottom spacer that is positioned vertically under the gate structure so as to thereby result in the formation of an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of a perimeter of the VOCS structure, and forming a replacement bottom spacer above the semiconductor substrate and adjacent the air gap.

公开(公告)号：US20180175202A1

公开(公告)日：2018-06-21

申请号：US15890880

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

公开(公告)号：US09935179B2

公开(公告)日：2018-04-03

申请号：US15472556

申请日：2017-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

公开(公告)号：US09935018B1

公开(公告)日：2018-04-03

申请号：US15436281

申请日：2017-02-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L21/823885 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and second vertical transistor devices, and forming first and second top spacers, respectively, around the first and second VOC structures, wherein the first spacer thickness is greater than the second spacer thickness. In this example, the method also includes performing at least one epitaxial deposition process to form a first top source/drain structure around the first VOC structure and above the first top spacer and a second top source/drain structure around the second VOC structure and above the second top spacer, and performing an anneal process so as to cause dopants in the first and second doped top source/drain structures to migrate into, respectively, the first and second VOC structures.

公开(公告)号：US09773885B2

公开(公告)日：2017-09-26

申请号：US15471733

申请日：2017-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US09680020B2

公开(公告)日：2017-06-13

申请号：US14794997

申请日：2015-07-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.

公开(公告)号：US09570466B2

公开(公告)日：2017-02-14

申请号：US14159027

申请日：2014-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ming Cai ,  Dechao Guo ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/84 ,  H01L29/78 ,  H01L27/13

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/13

Abstract: Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.

Abstract translation: 提供了在极薄的绝缘体上硅（ETSOI）晶圆上制造无源器件的技术。 在一方面，提供了一种用于在ETSOI晶片中制造一个或多个无源器件的方法。 该方法包括以下步骤。 提供具有衬底的ETSOI晶片和通过掩埋氧化物（BOX）与衬底分离的ETSOI层。 ETSOI层涂有保护层。 形成延伸穿过保护层，ETSOI层和BOX的至少一个沟槽，并且其中衬底的一部分暴露在沟槽内。 在沟槽的侧壁上形成间隔物。 从衬底模板化的外延硅在沟槽中生长。 保护层从ETSOI层去除。 无源器件形成在外延硅中。