公开(公告)号：US09960168B2

公开(公告)日：2018-05-01

申请号：US14582655

申请日：2014-12-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC: H01L21/20 ,  H01L27/108 ,  H01L21/324 ,  H01L21/84 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

公开(公告)号：US09773867B2

公开(公告)日：2017-09-26

申请号：US14962015

申请日：2015-12-08

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/06 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes first and second fins defined in a semiconductor substrate and a raised isolation post structure positioned between the first and second fins, wherein an upper surface of the raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface of each of the first and second fins. A first space is defined by a sidewall of the first fin and a first sidewall of the raised isolation post structure, a second space is defined by a sidewall of the second fin and a second sidewall of the raised isolation post structure, and a gate structure is positioned around a portion of each of the first and second fins and around a portion of the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces.

公开(公告)号：US09634004B2

公开(公告)日：2017-04-25

申请号：US15181992

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L23/31 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

公开(公告)号：US20170069627A1

公开(公告)日：2017-03-09

申请号：US15181992

申请日：2016-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L29/417 ,  H01L21/8234 ,  H01L23/31 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semicondcutor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

Abstract translation: 半切割器装置包括一对翅片上的钝化层。 阻挡层延伸穿过钝化层并在一对翅片之间并且电隔离散热片。 电触头通过钝化层形成到散热片。 电触点直接接触屏障的侧壁。

公开(公告)号：US09589849B2

公开(公告)日：2017-03-07

申请号：US14633353

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Bruce Doris ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/762 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.

Abstract translation: 本文公开的一种说明性方法包括形成多个初始翅片，其具有与基底相同的初始轴向长度和相同的初始应变，执行至少一个蚀刻工艺以将第一翅片切割成第一轴向 并且将第二翅片切割成小于第一轴向长度的第二轴向长度，其中切割的第一翅片保持初始应变的第一量，并且切割的第二翅片保持初始应变的约零或第二量 的初始应变小于第一量，并且围绕第一和第二切割翅片形成栅极结构以形成FinFET器件。

公开(公告)号：US09525027B2

公开(公告)日：2016-12-20

申请号：US14208518

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L21/225 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/1008 ,  H01L21/2254 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/4232 ,  H01L29/6625 ,  H01L29/66795 ,  H01L29/735 ,  H01L29/785

Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.

Abstract translation: 使用绝缘体上半导体衬底制造横向双极结晶体管。 晶体管包括在掺杂硅基区内的锗梯度，晶体管的集电极区域的方向上锗含量增加。 使用包括平行硅散热片的衬底来制造横向双极结晶体管有助于将CMOS FinFET器件和具有分级硅锗基极区域的横向双极结型晶体管包括在同一芯片上。

公开(公告)号：US20160293706A1

公开(公告)日：2016-10-06

申请号：US15186632

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.

Abstract translation: FinFET器件包括衬底，位于衬底上方的栅极结构以及邻近栅极结构定位的侧壁间隔物。 外延半导体材料位于FinFET器件的源极和漏极区域中，并且横向在侧壁间隔物的外侧。 翅片在FinFET器件的栅极长度方向上在栅极结构和侧壁间隔物之下横向延伸，其中鳍片的端面抵靠并接合外延半导体材料。 应力材料定位在位于翅片下方的衬底上方的通道腔中，并且横向地位于外延半导体材料之间，受压材料具有邻接并接合翅片的底表面的顶表面，邻接的底表面和 接合基板以及邻接和接合外延半导体材料的端面。

公开(公告)号：US09431306B2

公开(公告)日：2016-08-30

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/02 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域。

公开(公告)号：US09425319B2

公开(公告)日：2016-08-23

申请号：US14551606

申请日：2014-11-24

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。

公开(公告)号：US09425080B2

公开(公告)日：2016-08-23

申请号：US14600229

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Robert H. Dennard ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi

IPC: H01L21/762 ,  H01L27/115 ,  B82Y10/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/76251 ,  B82Y10/00 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11536 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.