公开(公告)号：US09343456B2

公开(公告)日：2016-05-17

申请号：US14477390

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Amaury Gendron-Hansen ,  Jagar Singh ,  Andy Wei

IPC: H01L27/02 ,  H01L29/739 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L21/285

CPC classification number: H01L21/28568 ,  H01L27/0255 ,  H01L29/42316 ,  H01L29/45 ,  H01L29/66356 ,  H01L29/7391

Abstract: A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side.

Abstract translation: 提供一种形成金属栅极二极管ESD保护器件的方法和所得到的器件。 实施例包括在基板上形成包括金属栅极的金属栅极二极管; 在所述金属栅极二极管的第一侧上形成n型阴极; 以及在所述金属栅极二极管的与所述第一侧相对的第二侧上形成p型阳极。

公开(公告)号：US09263520B2

公开(公告)日：2016-02-16

申请号：US14050494

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Ping Liu ,  Jing Wan ,  Andy Wei

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

Abstract translation: 提出了用于促进半导体器件的制造的方法，例如栅极全能纳米线场效应晶体管。 所述方法包括例如：提供至少一个堆叠结构，其包括在衬底结构上方延伸的至少一个层或凸块; 选择性地氧化所述至少一个堆叠结构的至少一部分以形成至少一个纳米线，所述至少一个纳米线在由所述堆叠结构的氧化材料包围的所述堆叠结构内延伸; 以及从所述堆叠结构中去除所述氧化的材料，暴露所述纳米线。 这种选择性氧化可以包括氧化衬底结构的上部，例如支撑堆叠结构的一个或多个翅片的上部，以促进纳米线的完全360度曝光。 在一个实施例中，堆叠结构包括一个或多个菱形凸块或凸脊。

公开(公告)号：US20150137194A1

公开(公告)日：2015-05-21

申请号：US14083604

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei

IPC: H01L29/417 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/76897 ,  H01L29/41791

Abstract: An inverted contact and methods of fabrication are provided. A sacrificial layer is patterned in an inverted trapezoid shape, and oxide is deposited around the pattern. The sacrificial layer is removed, and a metal contact material is deposited, taking an inverted-trapezoid shape. Embodiments of the present invention provide an inverted contact, having a wider base and a narrower top. The wider base provides improved electrical contact to the underlying active area. The narrower top allows for closer placement of adjacent contacts, serving to increase overall circuit density of an integrated circuit.

Abstract translation: 提供反向接触和制造方法。 牺牲层以倒梯形的形状图案化，并且氧化物沉积在图案周围。 去除牺牲层，沉积金属接触材料，呈倒梯形。 本发明的实施例提供了一种具有较宽底座和较窄顶部的倒置接触件。 较宽的基座提供与底层有效区域的改善的电接触。 较窄的顶部允许相邻触点的更靠近放置，用于增加集成电路的总体电路密度。

公开(公告)号：US20150076653A1

公开(公告)日：2015-03-19

申请号：US14028724

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC: H01L21/308 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。

公开(公告)号：US08962421B2

公开(公告)日：2015-02-24

申请号：US13678011

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gopal Srinivasan ,  Andy Wei ,  Dinesh Somasekhar ,  Ali Keshavarzi ,  Subi Kengeri

IPC: H01L21/8234 ,  H01L21/20 ,  H01L49/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L28/20 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78648

Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.

Abstract translation: 一种制造FinFET集成电路的方法包括在扩散区的第二端处沉积第一多晶硅层，在扩散区的第二端沉积第二多晶硅层; 将n型材料扩散到扩散区域中以形成扩散电阻器; 并且在所述第一和第二多晶硅层之间外延生长硅材料，以在所述扩散电阻器上方形成翅片结构并跨越所述第一和第二多晶硅层。

公开(公告)号：US20150050792A1

公开(公告)日：2015-02-19

申请号：US13965258

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth B. Samavedam ,  Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Nicholas V. LiCausi ,  Daniel Pham

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

Abstract translation: 公开了形成窄隔离区域的方法。 狭窄的隔离区域可以用作非常窄的扩散断裂，适用于3D FinFET技术。 在半导体衬底上形成衬垫氮化物层。 在衬垫氮化物层中形成腔体。 在腔中沉积保形间隔衬垫。 然后，各向异性蚀刻工艺在半导体衬底中形成沟槽。 沟槽足够窄，使得虚拟栅极完全覆盖沟槽。 然后可以在与虚拟栅极相邻的位置形成外延应力区域。 沟槽足够窄，使得在外延应力区域和沟槽之间存在间隙。

公开(公告)号：US20130126980A1

公开(公告)日：2013-05-23

申请号：US13718158

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

公开(公告)号：US09852984B2

公开(公告)日：2017-12-26

申请号：US15207652

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Sudharshanan Raghunathan

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

公开(公告)号：US09397004B2

公开(公告)日：2016-07-19

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

公开(公告)号：US09293586B2

公开(公告)日：2016-03-22

申请号：US13944048

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。