公开(公告)号：US08951873B2

公开(公告)日：2015-02-10

申请号：US13785480

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions.

Abstract translation: 提供了具有硅封装应力区域的半导体器件结构的装置和相关的制造方法。 一个半导体器件包括半导体衬底，覆盖半导体衬底的栅极结构，在栅极结构附近形成在半导体衬底中的应力区域以及覆盖在应力区域上的硅材料，所述硅材料封装应力区域。

公开(公告)号：US20140361335A1

公开(公告)日：2014-12-11

申请号：US13914288

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Gerd Zschaezsch

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.

Abstract translation: 一种器件包括衬底，P沟道晶体管和N沟道晶体管。 衬底包括第一半导体材料的第一层和第二半导体材料的第二层。 第一和第二半导体材料具有不同的晶格常数。 P沟道晶体管包括在衬底的第一部分中具有压应力的沟道区。 P沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 N沟道晶体管包括在衬底的第二部分中形成的具有拉伸应力的沟道区。 N沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 还公开了形成装置的方法。

公开(公告)号：US08735241B1

公开(公告)日：2014-05-27

申请号：US13747972

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Roman Boschke

IPC: H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

Abstract: Methods for forming CMOS integrated circuit structures are provided, the methods comprising performing a first implantation process for performing at least one of a halo implantation and a source and drain extension implantation into a region of a semiconductor substrate and then forming a stressor region in another region of the semiconductor substrate. Furthermore, a semiconductor device structure is provided, the structure comprising a stressor region embedded into a semiconductor substrate adjacent to a gate structure, the embedded stressor region having a surface differing along a normal direction of the surface from an interface by less than about 8 nm, wherein the interface is formed between the gate structure and the substrate.

Abstract translation: 提供了用于形成CMOS集成电路结构的方法，所述方法包括执行第一注入工艺，用于将光晕注入和源极和漏极延伸注入中的至少一个进行到半导体衬底的区域中，然后在另一区域中形成应力区域 的半导体衬底。 此外，提供了一种半导体器件结构，该结构包括嵌入到与栅极结构相邻的半导体衬底中的应力区域，所述嵌入的应力区域具有沿着表面的法线方向从界面相差小于约8nm的表面 其中所述界面形成在所述栅极结构和所述衬底之间。

公开(公告)号：US08673728B2

公开(公告)日：2014-03-18

申请号：US13667657

申请日：2012-11-02

Applicant: GlobalFoundries Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC: H01L21/20

CPC classification number: H01L28/20 ,  H01L29/78 ,  H01L29/7843

Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

Abstract translation: 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调谐电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。

公开(公告)号：US20130187209A1

公开(公告)日：2013-07-25

申请号：US13785480

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions.

Abstract translation: 提供了具有硅封装应力区域的半导体器件结构的装置和相关的制造方法。 一个半导体器件包括半导体衬底，覆盖半导体衬底的栅极结构，在栅极结构附近形成在半导体衬底中的应力区域以及覆盖在应力区域上的硅材料，所述硅材料封装应力区域。

公开(公告)号：US09685457B2

公开(公告)日：2017-06-20

申请号：US14805827

申请日：2015-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.

公开(公告)号：US09472642B2

公开(公告)日：2016-10-18

申请号：US14693978

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract translation: 本公开在一个方面中提供了半导体器件结构，其可以通过在半导体衬底内提供与在半导体衬底上形成的栅极结构对准的源极/漏极区域形成，其中栅极结构具有栅电极结构，第一 侧壁间隔件和第二侧壁间隔件，所述第一侧壁间隔物覆盖所述栅极电极结构和所述侧壁间隔物的侧壁表面，所述侧壁间隔件形成在所述第一侧壁间隔物上。 此外，形成半导体器件结构可以包括去除第二侧壁间隔物以暴露第一侧壁间隔物，在第一侧壁间隔物的一部分上形成第三侧壁间隔物，使得第一侧壁间隔物部分地暴露，并且形成硅化物区域 与源极/漏极区域中的第三侧壁间隔物对准。

公开(公告)号：US09425194B2

公开(公告)日：2016-08-23

申请号：US14819646

申请日：2015-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Abstract translation: 集成电路产品包括位于第一和第二有源区域中和之上的第一和第二晶体管。 第一晶体管具有第一栅极长度和第一栅极材料堆叠，其包括具有第一厚度的第一栅极电介质层和位于第一栅极介电层上方的至少一层金属，第一栅极介电层包括一层 第一高k绝缘材料和位于第一高k绝缘材料层上的第二高k绝缘材料层。 第二晶体管具有第二栅极长度和第二栅极材料堆叠，其包括具有位于第二有源区上方的第二厚度的第二栅极介电层和位于第二栅极介电层上方的至少一层金属，第二栅极电介质 层包括第二高k绝缘材料层。

公开(公告)号：US09343374B1

公开(公告)日：2016-05-17

申请号：US14527207

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Javorka ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.

Abstract translation: 形成包括在硅化之前拉回间隔物的多晶硅器件，并提供所得到的器件。 实施例包括在基板的上表面上形成两个多晶硅栅叠层; 在第二多晶硅栅叠层上形成硬掩模; 在所述第一多晶硅栅叠层的相对侧用硅帽形成eSiGe; 移除硬掩模; 在每个多晶硅栅极堆叠的相对侧形成氮化物间隔物; 在第二多晶硅栅叠层的相对侧形成深源极/漏极区; 在每个多晶硅栅极堆叠周围形成厚度小于距离基板的上表面的多晶硅栅叠层高度的厚度的填充层; 将氮化物间隔物的上部分除去湿间隙填充层的高度，然后除去湿间隙填充层; 并执行深源极/漏极区和硅帽的硅化。

公开(公告)号：US09257530B1

公开(公告)日：2016-02-09

申请号：US14471660

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschatzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76885 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract translation: 一个示例性实施例提供了制造集成电路的方法。 该方法包括在半导体衬底之上形成虚拟栅极结构，蚀刻在虚拟栅极结构之外的暴露的半导体衬底，在虚拟栅极结构和半导体衬底上沉积氧化硅以形成氧化硅层，蚀刻源极和漏极接触通孔 氧化硅层，通过源极和漏极接触通孔注入源极和漏极掺杂剂，去除虚拟栅极结构，形成最终的栅极结构，蚀刻基本上所有的氧化硅层，以及沉积超低K电介质以形成超 低K电介质层。