公开(公告)号：US20180138279A1

公开(公告)日：2018-05-17

申请号：US15351893

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Lars Wolfgang LIEBMANN ,  Hoon KIM

IPC: H01L29/417 ,  H01L29/772 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.

公开(公告)号：US20180130899A1

公开(公告)日：2018-05-10

申请号：US15343590

申请日：2016-11-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/785 ,  H01L21/2251 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. Prior to deposition of the conductive material, source/drain contact structures are recessed and a selective etch is used to remove sidewall spacers that are disposed between the source/drain contacts and the gate structures.

公开(公告)号：US20180130889A1

公开(公告)日：2018-05-10

申请号：US15345137

申请日：2016-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Hoon KIM ,  Chanro PARK

IPC: H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/45 ,  H01L29/665

Abstract: A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US20180012798A1

公开(公告)日：2018-01-11

申请号：US15689413

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L23/535 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US20170256455A1

公开(公告)日：2017-09-07

申请号：US15599026

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon KIM ,  Min-gyu SUNG ,  Ruilong XIE ,  Chanro PARK

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US20200312718A1

公开(公告)日：2020-10-01

申请号：US16367733

申请日：2019-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

公开(公告)号：US20200212192A1

公开(公告)日：2020-07-02

申请号：US16238173

申请日：2019-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Julien FROUGIER ,  Chanro PARK ,  Kangguo CHENG

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L23/535 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

Abstract: A device including a substrate and at least one fin formed over the substrate. At least one transistor is integrated with the fin at a top portion of the fin. The transistor includes an active region comprising a source, a drain and a channel region between the source and drain. A gate structure is formed over the channel region, and the gate structure includes a HKMG and air-gap spacers formed on opposite sidewalls of the HKMG. Each of the air-gap spacers includes an air gap that is formed along a trench silicide region, and the air-gap is formed below a top of the HKMG. A gate contact is formed over the active region.

公开(公告)号：US20200185266A1

公开(公告)日：2020-06-11

申请号：US16213189

申请日：2018-12-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE ,  Jessica M. DECHENE

IPC: H01L21/762 ,  H01L21/308 ,  H01L27/088 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

公开(公告)号：US20200119180A1

公开(公告)日：2020-04-16

申请号：US16160701

申请日：2018-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien FROUGIER ,  Ruilong XIE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.

公开(公告)号：US20200091143A1

公开(公告)日：2020-03-19

申请号：US16134173

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE ,  Laertis ECONOMIKOS

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.