公开(公告)号：US20090033351A1

公开(公告)日：2009-02-05

申请号：US11830368

申请日：2007-07-30

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858

摘要： A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.

公开(公告)号：US07287325B2

公开(公告)日：2007-10-30

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01K3/10

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US08003474B2

公开(公告)日：2011-08-23

申请号：US12192387

申请日：2008-08-15

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

IPC分类号： H01L21/33

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。

公开(公告)号：US20100038747A1

公开(公告)日：2010-02-18

申请号：US12192387

申请日：2008-08-15

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

IPC分类号： H01L21/768 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。

公开(公告)号：US07639032B2

公开(公告)日：2009-12-29

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US08446014B2

公开(公告)日：2013-05-21

申请号：US13531008

申请日：2012-06-22

申请人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

发明人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

IPC分类号： H01L23/48

CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

公开(公告)号：US06870263B1

公开(公告)日：2005-03-22

申请号：US09052688

申请日：1998-03-31

申请人： Lawrence A. Clevenger ,  Ronald G. Filippi ,  Mark Hoinkis ,  Jeffery L. Hurd ,  Roy C. Iggulden ,  Herbert Palm ,  Hans W. Poetzlberger ,  Kenneth P. Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim A. Mehter

发明人： Lawrence A. Clevenger ,  Ronald G. Filippi ,  Mark Hoinkis ,  Jeffery L. Hurd ,  Roy C. Iggulden ,  Herbert Palm ,  Hans W. Poetzlberger ,  Kenneth P. Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim A. Mehter

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

摘要翻译： 用于互连具有改进的可靠性的集成电路部件的导体。 导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。 已经发现，低纹理导体导致改善的电迁移寿命。

公开(公告)号：US06518670B1

公开(公告)日：2003-02-11

申请号：US10091643

申请日：2002-03-06

申请人： Jack A. Mandelman ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Richard A. Wachnik

发明人： Jack A. Mandelman ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Richard A. Wachnik

IPC分类号： H01L2940

CPC分类号： H01L21/76897 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines. A upper ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines. The resistive stud, the capacitor dielectric, and the intermediate conductor across the capacitor dielectric layer and the liner layer form an electrically porous, distributed resistive-capacitive low-pass decoupling network.

摘要翻译： 半导体器件包括互连的导体线，其包括在衬底上形成有顶表面的下层间介电层（ILD）层。 在由形成在下ILD层上的绝缘体围绕的下ILD层的顶表面上形成几个下导体线。 一组电阻螺柱中的每一个具有侧壁，下端和上端，并且在下端处连接到下导体线的顶部。 在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。 上导体线形成在上层。 每个具有与相应的一个电阻螺柱接触的底表面。 在中间导体下方形成中心ILD层，以将中间导线与下导体线电绝缘和分离。 上部ILD层覆盖中间导体，用于将中间导体线与上部导体线电绝缘和分离。 电阻螺柱，电容器电介质和跨过电容器电介质层和衬层的中间导体形成电多孔分布式电阻电容低通去耦网络。

公开(公告)号：US06383920B1

公开(公告)日：2002-05-07

申请号：US09757894

申请日：2001-01-10

申请人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

发明人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

IPC分类号： H01L214763

CPC分类号： H01L21/76847 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

摘要翻译： 本发明一般涉及在双镶嵌工艺中封闭通孔的方法。 在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽 在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。 或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在 双镶嵌工艺。 阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。

公开(公告)号：US20110193199A1

公开(公告)日：2011-08-11

申请号：US12702463

申请日：2010-02-09

申请人： Ronald G. Filippi ,  John A. Fitzsimmons ,  Kevin Kolvenbach ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  John A. Fitzsimmons ,  Kevin Kolvenbach ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。