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    METHOD FOR PRODUCING A PROTECTIVE STRUCTURE
    41.
    发明申请
    METHOD FOR PRODUCING A PROTECTIVE STRUCTURE 有权
    生产保护结构的方法

    公开(公告)号：US20140235039A1

    公开(公告)日：2014-08-21

    申请号：US14260301

    申请日：2014-04-24

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/22

    CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

    Abstract: A method for producing a protective structure may include: providing a semiconductor base substrate with a doping of a first conductivity type; producing a first epitaxial layer on the substrate; implanting a dopant of a second conductivity type in a delimited implantation region of the first epitaxial layer; applying a second epitaxial layer with a doping of the second conductivity type on the first epitaxial layer; forming an insulation zone in the second epitaxial layer, such that the second epitaxial layer is subdivided into first and second regions; producing a first dopant zone with a doping of the first conductivity type in the first region above the implantation region; producing a second dopant zone with a doping of the second conductivity type in the second region; outdiffusing the dopant from the implantation region to form a buried layer at the junction between the first epitaxial layer and the first region.

    Abstract translation: 制造保护结构的方法可以包括：提供具有第一导电类型的掺杂的半导体基底衬底; 在衬底上产生第一外延层; 在所述第一外延层的界定的注入区域中注入第二导电类型的掺杂剂; 在所述第一外延层上施加掺杂所述第二导电类型的第二外延层; 在所述第二外延层中形成绝缘区，使得所述第二外延层被细分成第一和第二区域; 在注入区域上方的第一区域中产生掺杂第一导电类型的第一掺杂区; 在所述第二区域中产生掺杂所述第二导电类型的第二掺杂区; 从注入区域向外扩散掺杂剂以在第一外延层和第一区域之间的结处形成掩埋层。

    PROTECTIVE STRUCTURE
    42.
    发明申请
    PROTECTIVE STRUCTURE 有权
    保护结构

    公开(公告)号：US20130341771A1

    公开(公告)日：2013-12-26

    申请号：US14011885

    申请日：2013-08-28

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

    IPC: H01L29/868 ,  H01L29/66

    CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

    Abstract: A protective structure may include: a semiconductor substrate having a doping of a first conductivity type; a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate; a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate; a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer; a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer; an electrical insulation arranged between the first region and the second region of the semiconductor layer; and a common connection device for the first dopant zone and the second dopant zone.

    Abstract translation: 保护结构可以包括：具有第一导电类型的掺杂的半导体衬底; 具有布置在所述半导体衬底的表面处的第二导电类型的掺杂的半导体层; 具有布置在所述半导体层的第一区域中以及所述半导体层和所述半导体衬底之间的接合处的掺杂所述第二导电类型的掩埋层; 第一掺杂区，其具有布置在所述半导体层的所述第一区域之上的所述第一导电类型的掺杂; 具有布置在所述半导体层的第二区域中的所述第二导电类型的掺杂的第二掺杂区; 布置在半导体层的第一区域和第二区域之间的电绝缘体; 以及用于第一掺杂区和第二掺杂区的公共连接装置。

    Integrated Circuits With Magnetic Core Inductors And Methods of Fabrications Thereof
    43.
    发明申请
    Integrated Circuits With Magnetic Core Inductors And Methods of Fabrications Thereof 有权
    具有磁芯电感器的集成电路及其制造方法

    公开(公告)号：US20130260483A1

    公开(公告)日：2013-10-03

    申请号：US13903935

    申请日：2013-05-28

    Applicant: Infineon Technologies AG

    Inventor： Renate Hofmann ,  Carsten Ahrens ,  Wolfgang Klein ,  Alexander Glas

    IPC: H01L49/02

    CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/0066 ,  H01L23/5227 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

    Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底之内和/或之上形成第一电感线圈。 第一电感线圈形成在衬底的顶侧附近。 第一沟槽形成在与第一电感线圈相邻的衬底内。 至少部分地用磁性填充材料填充第一沟槽。 至少第一电感线圈下面的衬底的第一部分变薄。 背面磁性层形成在基板的第一部分之下。 背面磁性层和磁性填充材料形成第一电感线圈的磁芯区域的至少一部分。

    Method of Fabricating a Semiconductor Device
    44.
    发明公开
    Method of Fabricating a Semiconductor Device 审中-公开

    公开(公告)号：US20240038848A1

    公开(公告)日：2024-02-01

    申请号：US18484966

    申请日：2023-10-11

    Applicant: Infineon Technologies AG

    Inventor： Helmut Brech ,  Carsten Ahrens ,  Matthias Zigldrum

    IPC: H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778

    CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L29/78 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

    Abstract: A method of fabricating a semiconductor device includes: epitaxially growing a multilayer Group-III nitride structure on a first surface of a substrate; removing portions of the multilayer structure to form a mesa arranged on the first surface; applying insulating material to the first surface of the substrate so that side faces of the mesa are embedded in the insulating material; forming an electrode on a top surface of the mesa; forming a via in the insulating material that extends from the top surface of the insulating material to the first surface of the substrate; inserting conductive material into the via to form a conductive via; applying an electrically conductive redistribution structure to the upper surface and electrically connecting the conductive via to the electrode; and successively removing portions of a second surface of the substrate, to expose the insulating material and form a worked second surface including the insulating material.

    RF module
    46.
    发明授权
    RF module 有权

    公开(公告)号：US10128204B2

    公开(公告)日：2018-11-13

    申请号：US15730466

    申请日：2017-10-11

    Applicant: Infineon Technologies AG

    Inventor： Carsten Ahrens ,  Katharina Umminger ,  Carsten von Koblinski

    IPC: H01L21/70 ,  H01L23/66 ,  H01L23/522 ,  H01L23/64 ,  H01L25/11

    Abstract: In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main surface region of the bulk semiconductor substrate; an insulator structure surrounding a side surface region of the bulk semiconductor substrate; a wiring layer stack including at least one structured metallization layer embedded into an insulation material, the wiring layer stack being arranged on the first main surface region of the bulk semiconductor substrate and a first main surface region of the insulator structure; and a carrier structure at a second main surface region of the insulator structure, wherein the carrier structure and the insulator structure include different materials.

    Arrangement and method for manufacturing the same
    50.
    发明授权
    Arrangement and method for manufacturing the same 有权
    其制造方法及其制造方法

    公开(公告)号：US09196568B2

    公开(公告)日：2015-11-24

    申请号：US14042750

    申请日：2013-10-01

    Applicant: Infineon Technologies AG

    Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

    IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

    CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

    Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

    Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

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