公开(公告)号：US20150076672A1

公开(公告)日：2015-03-19

申请号：US14028577

申请日：2013-09-17

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法可以包括电接触至少一个第一芯片，第一芯片包括第一侧和与第一侧相对的第二侧，其第二侧为导电载体。 绝缘层形成在导电载体的至少一部分上并且在芯片的第一侧的至少一部分上方。 至少一个第二芯片布置在绝缘层上。 在第一芯片和第二芯片上形成封装材料。 电触头通过封装材料形成至少一个第一芯片和至少一个第二芯片的至少一个触点的至少一个触点。

公开(公告)号：US20150028448A1

公开(公告)日：2015-01-29

申请号：US13951556

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L25/065 ,  H01L23/12 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16265 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure.

Abstract translation: 芯片封装包括导电芯片载体和连接到导电芯片载体的至少一个第一半导体芯片。 芯片封装进一步包括无源元件。 导电芯片载体，至少一个第一半导体芯片和无源部件被嵌入绝缘层压结构中。

公开(公告)号：US20140197527A1

公开(公告)日：2014-07-17

申请号：US13742455

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/495 ,  H01L21/77

CPC classification number: H01L21/4807 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/77 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/743 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 电连接到所述载体的第一芯片; 布置在所述载体上的陶瓷层; 以及设置在所述陶瓷层上的第二芯片; 其中所述陶瓷层的孔隙率在约3％至约70％的范围内。