公开(公告)号：US11151074B2

公开(公告)日：2021-10-19

申请号：US16542085

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Roni Rosner ,  Ravi Venkatesan ,  Shlomi Shua ,  Oz Shitrit ,  Henrietta Bezbroz ,  Alexander Gendler ,  Ohad Falik ,  Zigi Walter ,  Michael Behar ,  Shlomi Alkalay

IPC: G06F13/42 ,  G06N3/04 ,  G06F13/20 ,  G06F12/0893

Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.

公开(公告)号：US20210294641A1

公开(公告)日：2021-09-23

申请号：US17342476

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  William A. Braun ,  Rajshree A. Chabukswar ,  Leigh Davies ,  Russell J. Fenger ,  Alexander Gendler ,  Raoul V. Rivas Toledano ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.

公开(公告)号：US11106271B2

公开(公告)日：2021-08-31

申请号：US16572747

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Arkady Bramnik ,  Lev Makovsky

IPC: G06F1/32 ,  G06F1/3287 ,  G06F11/10 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3296

Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.

公开(公告)号：US10775434B2

公开(公告)日：2020-09-15

申请号：US16142591

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Larisa Novakovsky ,  Edward Brazil ,  Alexander Gendler

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/3203 ,  G06F11/27

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

公开(公告)号：US10365707B2

公开(公告)日：2019-07-30

申请号：US15374684

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US10289188B2

公开(公告)日：2019-05-14

申请号：US15188303

申请日：2016-06-21

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Henrietta Bezbroz

IPC: G06F13/24 ,  G06F1/3287 ,  G06F9/4401

Abstract: In one embodiment, a processor includes: a plurality of cores, at least some having an advanced programmable interrupt controller (APIC) identifier associated therewith; a plurality of power management agents associated with the plurality of cores; and a power controller to receive an indication of an interrupt and a first APIC identifier and send a wake signal and the first APIC identifier to the plurality of power management agents to determine which of the plurality of cores is associated with the first APIC identifier. Other embodiments are described and claimed.

公开(公告)号：US10268255B2

公开(公告)日：2019-04-23

申请号：US15197083

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Efraim Rotem ,  Alexander Gendler ,  Ankush Varma

IPC: G06F1/26 ,  G06F1/28 ,  G06F9/38 ,  G06F9/44 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/329

Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.

公开(公告)号：US10198027B2

公开(公告)日：2019-02-05

申请号：US15370207

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ariel Szapiro ,  Mark Gutman

IPC: G06F1/12 ,  G06F1/32

Abstract: In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.

公开(公告)号：US09910470B2

公开(公告)日：2018-03-06

申请号：US14970747

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

公开(公告)号：US20170364132A1

公开(公告)日：2017-12-21

申请号：US15182990

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.