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    OPTICAL INTERCONNECT ON BUMPLESS BUILD-UP LAYER PACKAGE
    42.
    发明申请
    OPTICAL INTERCONNECT ON BUMPLESS BUILD-UP LAYER PACKAGE 审中-公开
    无障碍建筑层包装的光学互连

    公开(公告)号：US20160254641A1

    公开(公告)日：2016-09-01

    申请号：US15056794

    申请日：2016-02-29

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

    IPC: H01S5/022 ,  H01S5/183

    CPC classification number: H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

    Abstract: This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

    Abstract translation: 本公开一般涉及一种电子封装，其可以包括至少部分地包封管芯的管芯和电介质层。 电互连可以电耦合到管芯并且至少部分地通过电介质层。 光发射器可以用电互连的第一个电耦合到管芯，并且被配置为从电子封装的第一主表面发射光。 焊料凸块可以用电互连的第二个电耦合到管芯，并且位于电子封装的不同于第一主表面的第二主表面上。

    SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS
    43.
    发明申请
    SELECTIVE LAYER TRANSFER PROCESS IMPROVEMENTS 有权

    公开(公告)号：US20250112218A1

    公开(公告)日：2025-04-03

    申请号：US18478831

    申请日：2023-09-29

    Applicant: Intel Corporation

    Inventor： Brandon M. Rawlings ,  Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Kimin Jun ,  Johanna Swan ,  Richard F. Vreeland

    IPC: H01L25/00 ,  H01L21/683 ,  H01L25/075

    Abstract: In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. The process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of IC components on the first substrate to respective bonding structures on the third substrate.

    Thermal management solutions for embedded integrated circuit devices
    44.
    发明授权
    Thermal management solutions for embedded integrated circuit devices 有权

    公开(公告)号：US12142543B2

    公开(公告)日：2024-11-12

    申请号：US18092140

    申请日：2022-12-30

    Applicant: INTEL CORPORATION

    Inventor： Johanna Swan ,  Feras Eid ,  Adel Elsherbini

    IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H01L23/498

    Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat dissipation device in thermal contact with the integrated circuit device, wherein a first portion of the heat dissipation device extends into the substrate and wherein a second portion of the heat dissipation device extends over the substrate. In one embodiment, the heat dissipation device may comprise the first portion of the heat dissipation device formed from metallization within the substrate.

    POROUS MESH STRUCTURES FOR THE THERMAL MANAGEMENT OF INTEGRATED CIRCUIT DEVICES
    47.
    发明公开
    POROUS MESH STRUCTURES FOR THE THERMAL MANAGEMENT OF INTEGRATED CIRCUIT DEVICES 审中-公开

    公开(公告)号：US20230317549A1

    公开(公告)日：2023-10-05

    申请号：US17709064

    申请日：2022-03-30

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Wenhao Li ,  Paul Diglio ,  Xavier Brun ,  Johanna Swan

    IPC: H01L23/373 ,  H01L21/48

    CPC classification number: H01L23/3733 ,  H01L21/4871

    Abstract: A porous mesh structure for use in the thermal management of integrated circuit devices may be formed as a solid matrix with a plurality of pores dispersed therein, wherein the solid matrix may be a plurality of fused matrix material particles and the plurality of pores may comprise between about 10% and 90% of a volume of the porous mesh structure. The porous mesh structure may be formed on an integrated circuit device and/or on a heat dissipation assembly component, and may be incorporated into an immersion cooling assembly, wherein the porous mesh structure may act as a nucleation site for a working fluid in the immersion cooling assembly.

    Thermal management solutions for stacked integrated circuit devices
    50.
    发明授权
    Thermal management solutions for stacked integrated circuit devices 有权

    公开(公告)号：US11482472B2

    公开(公告)日：2022-10-25

    申请号：US16007260

    申请日：2018-06-13

    Applicant: Intel Corporation

    Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

    IPC: H01L23/473 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/467 ,  H01L23/13 ,  H01L23/00 ,  H01L21/48

    Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

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