公开(公告)号：US11815979B2

公开(公告)日：2023-11-14

申请号：US16633120

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Yoni Aizik ,  Esfir Natanzon ,  Nir Rosenzweig ,  Nadav Shulman ,  Bart Plackle

IPC: G06F1/329 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F9/4893

Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.

公开(公告)号：US11175712B2

公开(公告)日：2021-11-16

申请号：US16527150

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26 ,  G06F1/3296

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US20200225723A1

公开(公告)日：2020-07-16

申请号：US16833328

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Oren Zonensain ,  Roman Rechter ,  Almog Reshef ,  Maxim Levit ,  Nadav Shulman ,  Efraim Rotem

IPC: G06F1/28 ,  G01R31/52

Abstract: A performance management scheme for a processor based on leakage current measurement in field. The scheme performs the operations of detection and correction. The operation of detection measures per core leakage current in the field (e.g., using voltage regulator electrical current counters). The operation of correction changes the processor power management behavior. For example, processor cores showing high leakage degradation may be logically swapped with cores showing low leakage degradation.

公开(公告)号：US20200174541A1

公开(公告)日：2020-06-04

申请号：US16206019

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Michael Bitan ,  Andrey Gabdulin ,  Efraim Rotem ,  Eli Efron ,  Nadav Shulman ,  David Ben Shimon ,  Nir Levitin ,  Esfir Natanzon

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/20

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

公开(公告)号：US10345889B2

公开(公告)日：2019-07-09

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/07

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US10324519B2

公开(公告)日：2019-06-18

申请号：US15190377

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Efraim Rotem ,  Yoni Aizik ,  Doron Rajwan ,  Gal Leibovich ,  Nadav Shulman ,  Hisham Abu Salah

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F13/24

Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20190121423A1

公开(公告)日：2019-04-25

申请号：US16223818

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/084 ,  G06F12/0802 ,  G06F1/28 ,  G06F12/0864 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190121422A1

公开(公告)日：2019-04-25

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/084 ,  G06F12/0802 ,  G06F1/28 ,  G06F12/0864 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190011976A1

公开(公告)日：2019-01-10

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/32

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314307A1

公开(公告)日：2018-11-01

申请号：US15966397

申请日：2018-04-30

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/28 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.