公开(公告)号：US11128555B2

公开(公告)日：2021-09-21

申请号：US15655874

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Daniel Rivas Barragan ,  John Chun Kwok Leung ,  Mark S. Myers ,  Suraj Prabhakaran ,  Murugasamy K. Nachimuthu ,  Slawomir Putyrski

IPC: G06F15/177 ,  H04L12/26 ,  G06F16/22 ,  G06F16/23 ,  H04L12/24 ,  H04L12/927 ,  H04Q9/00 ,  H04L29/08 ,  H04L12/925

Abstract: Techniques for migration for composite nodes in software-defined infrastructures (SDI) are described. A SDI system may include a SDI manager component, including one or more processor circuits, configured to access one or more remote resources, the SDI manager component may include a partition manager configured to receive a request to create a composite node from an orchestrator component, the request including at least one preferred compute sled type and at least one alternative compute sled type. The SDI manager may create a composite node using a first compute sled matching the at least one alternative compute sled type. The SDI manager may determine, based upon a migration table stored on a non-transitory computer-readable storage medium that a second compute sled matching the at least one preferred compute sled type is available. The SDI manager may perform an migration from the first compute sled to the second compute sled. Other embodiments are described and claimed.

公开(公告)号：US11029870B2

公开(公告)日：2021-06-08

申请号：US15721829

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F15/80 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14 ,  H04L12/911 ,  G06F11/14 ,  H04L29/06

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

公开(公告)号：US20210141552A1

公开(公告)日：2021-05-13

申请号：US17125420

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry Mitchel ,  Rahul Khanna ,  Slawomir Putyrski ,  Sujoy Sen ,  Paul Dormitzer

IPC: G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H01R13/453 ,  G06F9/48 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/631 ,  H05K7/14

Abstract: Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed.

公开(公告)号：US20200341810A1

公开(公告)日：2020-10-29

申请号：US16392822

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Narayan Ranganathan ,  Sujoy Sen ,  Joseph Grecco ,  Slawomir Putyrski

IPC: G06F9/50

Abstract: Technologies for providing an accelerator device discovery service include a device having circuitry configured to obtain, from a discovery service, availability data indicative of a set of accelerator devices available to assist in the execution of a workload. The circuitry is also configured to select, as a function of the availability data, one or more target accelerator devices to assist in the execution of the workload, and execute the workload with the one or more target accelerator devices.

公开(公告)号：US10678737B2

公开(公告)日：2020-06-09

申请号：US16235982

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Slawomir Putyrski ,  Joseph Grecco ,  Evan Custodio ,  Francesc Guim Bernat

IPC: G06F13/40 ,  G06F9/4401

Abstract: Technologies for providing dynamic communication path modification for accelerator device kernels include an accelerator device comprising circuitry to obtain initial availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also to produce, as a function of the initial availability data, a connectivity matrix indicative of the physical communication paths and a logical communication path defined by one or more of the physical communication paths between a kernel of the present accelerator device and a target accelerator device kernel. Additionally, the circuitry is to obtain updated availability data indicative of a subsequent availability of each accelerator device kernel and update, as a function of the updated availability data, the connectivity matrix to modify the logical communication path.

公开(公告)号：US10404547B2

公开(公告)日：2019-09-03

申请号：US15114687

申请日：2015-02-24

Applicant: INTEL CORPORATION

Inventor： Katalin K. Bartfai-Walcott ,  Michael Christopher Woods ,  Giovani Estrada ,  John Kennedy ,  Joseph Butler ,  Slawomir Putyrski ,  Alexander Leckey ,  Victor M. Bayon-Molino ,  Connor Upton ,  Thijs Metsch

IPC: G06F15/173 ,  H04L12/24 ,  H04L12/26

Abstract: Technologies for datacenter management include one or more computing racks each including a rack controller. The rack controller may receive system, performance, or health metrics for the components of the computing rack. The rack controller generates regression models to predict component lifespan and may predict logical machine lifespans based on the lifespan of the included hardware components. The rack controller may generate notifications or schedule maintenance sessions based on remaining component or logical machine lifespans. The rack controller may compose logical machines using components having similar remaining lifespans. In some embodiments the rack controller may validate a service level agreement prior to executing an application based on the probability of component failure. A management interface may generate an interactive visualization of the system state and optimize the datacenter schedule based on optimization rules derived from human input in response to the visualization. Other embodiments are described and claimed.

公开(公告)号：US20190138481A1

公开(公告)日：2019-05-09

申请号：US16235982

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Slawomir Putyrski ,  Joseph Grecco ,  Evan Custodio ,  Francesc Guim Bernat

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F9/4401

Abstract: Technologies for providing dynamic communication path modification for accelerator device kernels include an accelerator device comprising circuitry to obtain initial availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also to produce, as a function of the initial availability data, a connectivity matrix indicative of the physical communication paths and a logical communication path defined by one or more of the physical communication paths between a kernel of the present accelerator device and a target accelerator device kernel. Additionally, the circuitry is to obtain updated availability data indicative of a subsequent availability of each accelerator device kernel and update, as a function of the updated availability data, the connectivity matrix to modify the logical communication path.

公开(公告)号：US20190065290A1

公开(公告)日：2019-02-28

申请号：US15859365

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Evan Custodio ,  Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry MItchel

IPC: G06F9/54 ,  G02B6/44 ,  H03K19/0175

Abstract: Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.

公开(公告)号：US20190065253A1

公开(公告)日：2019-02-28

申请号：US15859370

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Slawomir Putyrski ,  Rahul Khanna ,  Paul Dormitzer

IPC: G06F9/48 ,  G06N5/02

Abstract: Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.

公开(公告)号：US20180150334A1

公开(公告)日：2018-05-31

申请号：US15719770

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry MItchel ,  Rahul Khanna ,  Slawomir Putyrski ,  Sujoy Sen ,  Paul Dormitzer

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed