公开(公告)号：US11348909B2

公开(公告)日：2022-05-31

申请号：US16146445

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Maruti Gupta Hyde ,  Nageen Himayat ,  Linda Hurd ,  Min Suet Lim ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F1/3203 ,  H01L25/10 ,  G06F1/3296 ,  G06F1/3237 ,  G06F1/324 ,  H01L25/16 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3287

Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.

公开(公告)号：US11320883B2

公开(公告)日：2022-05-03

申请号：US16146463

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/3203 ,  G06F1/3234 ,  H01L25/16 ,  G06N3/063 ,  H01L25/065 ,  G06F1/20 ,  H01L25/18 ,  G06N3/04 ,  G06N3/08

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example multi-die package includes a computer processor unit (CPU) die, a memory die stacked in vertical alignment with the CPU die, and artificial intelligence (AI) architecture circuitry to infer a workload for at least one of the CPU die or the memory die. The AI architecture circuitry is to manage power consumption of at least one of the CPU die or the memory die based on the inferred workload.

公开(公告)号：US20210408291A1

公开(公告)日：2021-12-30

申请号：US16914172

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L27/22 ,  H01L27/24 ,  H01L29/66

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20210408002A1

公开(公告)日：2021-12-30

申请号：US16914152

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Travis W. LaJoie ,  Abhishek A. Sharma ,  Van Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Bernhard Sell ,  Juan G. Alzate-Vinasco

IPC: H01L27/108

Abstract: An integrated circuit capacitor array includes a plurality of first electrodes, wherein individual ones of the first electrodes are substantially cylindrical with a base over a substrate and an open top end over the base. A first dielectric material layer spans a distance between the first electrodes but is absent from an interior of the first electrodes, where the first dielectric material layer is substantially planar and bifurcates a height of first electrodes. A second dielectric material layer lines the interior of the first electrodes, and lines portions of an exterior of the first electrodes above and below the first dielectric material layer and a second electrode is within the interior of the first electrodes and is around the exterior of the first electrodes above and below the first dielectric material layer.

公开(公告)号：US11205630B2

公开(公告)日：2021-12-21

申请号：US16586158

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US11094672B2

公开(公告)日：2021-08-17

申请号：US16586145

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

公开(公告)号：US10784170B2

公开(公告)日：2020-09-22

申请号：US16372272

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: H01L21/84 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/205

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20190305133A1

公开(公告)日：2019-10-03

申请号：US15942175

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Gilbert Dewey ,  Van Le ,  Jack Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L21/425

Abstract: A thin film transistor (TFT) device is provided, where the TFT may include a source and a drain, a gate stack, and a semiconductor body. The gate stack may include a gate dielectric structure and a gate electrode, and the gate stack may be between the source and the drain. A first section of the semiconductor body may be adjacent to at least a section of the gate stack. A spacer may be between the gate stack and the source, where the spacer may be on the semiconductor body, and where a second section of the semiconductor body underneath the spacer may comprise dopants.

公开(公告)号：US20190051642A1

公开(公告)日：2019-02-14

申请号：US16146445

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Maruti Gupta Hyde ,  Nageen Himayat ,  Linda Hurd ,  Min Suet Lim ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367 ,  G06F1/32 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.

公开(公告)号：US09029835B2

公开(公告)日：2015-05-12

申请号：US13721759

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Benjamin Chu-King ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Nitika Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L29/06

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

Abstract translation: 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全面的栅极”结构。 本文描述了其它实施例。