公开(公告)号：US20200227520A1

公开(公告)日：2020-07-16

申请号：US16831692

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. CEA ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

公开(公告)号：US20200006523A1

公开(公告)日：2020-01-02

申请号：US16024699

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Jessica TORRES ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI

IPC: H01L29/66 ,  H01L21/02

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate with a surface that is substantially flat. A channel area including an III-V compound may be above the substrate, where the channel area is an epitaxial layer directly in contact with the surface of the substrate. A gate dielectric layer is adjacent to the channel area and in direct contact with the channel area, while a gate electrode is adjacent to the gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393214A1

公开(公告)日：2019-12-26

申请号：US16017971

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/02

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

公开(公告)号：US20190296145A1

公开(公告)日：2019-09-26

申请号：US16316337

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Sean T. MA ,  Harold KENNEL

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

公开(公告)号：US20190214461A1

公开(公告)日：2019-07-11

申请号：US16358613

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/786 ,  H01L21/3115

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20190103486A1

公开(公告)日：2019-04-04

申请号：US16099532

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L23/31 ,  H01L23/29

Abstract: An apparatus including a transistor device including a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel includes a length dimension between source and drain that is greater than a length dimension of the gate electrode such that there is a passivated underlap between an edge of the gate electrode and an edge of the channel relative to each of the source and the drain. A method including forming a channel of a transistor device on a substrate; forming first and second passivation layers on a surface of substrate on opposite sides of the channel; forming a gate stack on the channel between first and second passivation layers; and forming a source on the substrate between the channel and the first passivation layer and a drain on the substrate between the channel and the second passivation layer.

公开(公告)号：US20180315827A1

公开(公告)日：2018-11-01

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Matthew V. METZ ,  Chandra S. MOHAPATRA ,  Gilbert DEWEY ,  Nadia M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US20180261498A1

公开(公告)日：2018-09-13

申请号：US15779442

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

公开(公告)号：US20180226496A1

公开(公告)日：2018-08-09

申请号：US15771998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/267 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/107 ,  H01L29/1079 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

公开(公告)号：US20180204947A1

公开(公告)日：2018-07-19

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.