公开(公告)号：US10229975B2

公开(公告)日：2019-03-12

申请号：US15613930

申请日：2017-06-05

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  ChoongHyun Lee ,  Shogo Mochizuki ,  Koji Watanabe

IPC: H01L21/336 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L21/324 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.

公开(公告)号：US20180337277A1

公开(公告)日：2018-11-22

申请号：US15905891

申请日：2018-02-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  ChoongHyun Lee ,  Shogo Mochizuki ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：US10128372B1

公开(公告)日：2018-11-13

申请号：US15905891

申请日：2018-02-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  ChoongHyun Lee ,  Shogo Mochizuki ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L29/0649 ,  H01L29/41741 ,  H01L29/6656 ,  H01L29/66666

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：US20180277656A1

公开(公告)日：2018-09-27

申请号：US15468755

申请日：2017-03-24

Applicant: International Business Machines Corporation

Inventor： Robin H. Chao ,  ChoongHyun Lee ,  Chun W. Yeung ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66553 ,  H01L21/02332 ,  H01L21/02337 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7853

Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having uniform low-k inner spacers. A nanosheet stack is formed opposite a major surface of a substrate. The nanosheet stack includes multiple nanosheets. Cavities are formed between adjacent ones of the multiple nanosheets. The cavities are filled with an oxide material and portions of the oxide material are nitridized to form inner spacers positioned between the adjacent ones of the multiple nanosheets.

公开(公告)号：US20180211885A1

公开(公告)日：2018-07-26

申请号：US15412499

申请日：2017-01-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/311

CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L27/092

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.

公开(公告)号：US10002791B1

公开(公告)日：2018-06-19

申请号：US15481012

申请日：2017-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

公开(公告)号：US12255106B2

公开(公告)日：2025-03-18

申请号：US17527355

申请日：2021-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Takashi Ando ,  ChoongHyun Lee ,  Alexander Reznicek

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.

公开(公告)号：US20230282728A1

公开(公告)日：2023-09-07

申请号：US18317165

申请日：2023-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  ChoongHyun Lee ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Heng Wu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66522 ,  H01L21/02546 ,  H01L21/3065 ,  H01L21/02609 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/78696 ,  H01L29/42392 ,  H01L21/02532 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

公开(公告)号：US11251285B2

公开(公告)日：2022-02-15

申请号：US16553912

申请日：2019-08-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/324 ,  H01L21/02 ,  H01L29/49

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

公开(公告)号：US11217450B2

公开(公告)日：2022-01-04

申请号：US16582315

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Vijay Narayanan

IPC: H01L29/161 ,  H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/84 ,  H01L29/49 ,  H01L29/78

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.