公开(公告)号：US20170194196A1

公开(公告)日：2017-07-06

申请号：US15467665

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Markus Brink ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76807 ,  G03F7/0002 ,  H01L21/02118 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.

公开(公告)号：US09530876B2

公开(公告)日：2016-12-27

申请号：US14135668

申请日：2013-12-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

Abstract translation: 在绝缘体层上形成由一对半导体焊盘部分横向邻接的至少一个半导体纳米线。 从至少一个半导体纳米线下方蚀刻绝缘体层的一部分，使得至少一个半导体纳米线被悬浮。 临时填充材料沉积在至少一个半导体纳米线上，并且被平坦化以物理地暴露该对半导体焊盘部分的顶表面。 沟槽形成在该对半导体焊盘部分内，并且填充有应力产生材料。 随后取出临时填充材料。 所述至少一个半导体纳米线在拉伸应变或压缩应变下沿长度方向应变。

公开(公告)号：US09157887B2

公开(公告)日：2015-10-13

申请号：US13966427

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336 ,  G01N27/414 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/16 ,  H01L51/00

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a sensor includes forming a channel in substrate, forming a sacrificial layer in the channel, forming a sensor having a first dielectric layer disposed on the substrate, a graphene layer disposed on the first dielectric layer, and a second dielectric layer disposed on the graphene layer, a source region, a drain region, and a gate region, wherein the gate region is disposed on the sacrificial layer removing the sacrificial layer from the channel.

Abstract translation: 一种用于形成传感器的方法，包括在衬底中形成通道，在通道中形成牺牲层，形成具有设置在衬底上的第一介电层的传感器，设置在第一电介质层上的石墨烯层，以及设置在第二电介质层 在石墨烯层上，源区域，漏极区域和栅极区域，其中栅极区域设置在牺牲层上，从沟道去除牺牲层。

公开(公告)号：US08969187B2

公开(公告)日：2015-03-03

申请号：US13859284

申请日：2013-04-09

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Wilfried E. A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

公开(公告)号：US20140332892A1

公开(公告)日：2014-11-13

申请号：US13891873

申请日：2013-05-10

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey N. Sleight

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: At least one semiconductor fin is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor fin. The amount of the etched portions of the insulator is selected such that a metallic gate electrode layer fills the entire gap between the recessed surfaces of the insulator layer and the bottom surface(s) of the at least one semiconductor fin. An interface between the metallic gate electrode layer and a semiconductor gate electrode layer contiguously extends over the at least one semiconductor fin and does not underlie any of the at least one semiconductor fin. During patterning of a gate electrode, removal of the semiconductor material in the semiconductor gate electrode layer can be facilitated because the semiconductor gate electrode layer is not present under the at least one semiconductor fin.

公开(公告)号：US08871626B2

公开(公告)日：2014-10-28

申请号：US13649284

申请日：2012-10-11

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: FinFETS and methods for making FinFETs with a vertical silicide structure. A method includes providing a substrate with a plurality of fins, forming a gate stack above the substrate wherein the gate stack has at least one sidewall and forming an off-set spacer adjacent the gate stack sidewall. The method also includes growing an epitaxial film which merges the fins to form an epi-merge layer, forming a field oxide layer adjacent to at least a portion of the off-set spacer and removing a portion of the field oxide layer to expose a portion of the epi-merge-layer. The method further includes removing at least part of the exposed portion of the epi-merge-layer to form an epi-merge sidewall and an epi-merge spacer region and forming a silicide within the epi-merge sidewall to form a silicide layer and two silicide sidewalls.

Abstract translation: FinFET和用于制造具有垂直硅化物结构的FinFET的方法。 一种方法包括提供具有多个翅片的基板，在基板上形成栅极堆叠，其中栅极堆叠具有至少一个侧壁并形成邻近栅极堆叠侧壁的偏置间隔物。 该方法还包括生长外延膜，其将翅片合并以形成外延合并层，形成与偏置间隔物的至少一部分相邻的场氧化物层，并去除场氧化物层的一部分以暴露部分 的外延合并层。 该方法还包括去除外延合并层的暴露部分的至少一部分以形成外延合并侧壁和外延合并间隔区，并在外延合并侧壁内形成硅化物以形成硅化物层和二 硅化物侧壁

公开(公告)号：US20140312419A1

公开(公告)日：2014-10-23

申请号：US13865519

申请日：2013-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Thomas N. Adam ,  Veeraraghavan S. Basker ,  Jinghong Li ,  Chung-Hsun Lin ,  Sebastian Naczas ,  Alexander Reznicek ,  Tenko Yamashita

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A plurality of semiconductor fins are formed which extend from a semiconductor material portion that is present atop an insulator layer of a semiconductor-on-insulator substrate. A gate structure and adjacent gate spacers are formed that straddle each semiconductor fin. Portions of each semiconductor fin are left exposed. The exposed portions of the semiconductor fins are then merged by forming an epitaxial semiconductor material from an exposed semiconductor material portion that is not covered by the gate structure and gate spacers.

公开(公告)号：US20140310676A1

公开(公告)日：2014-10-16

申请号：US14317013

申请日：2014-06-27

Applicant: International Business Machines Corporation

Inventor： Wilfried Ernest-August Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Hailing Wang ,  Richard Q. Williams

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F17/5036

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个鳍片。该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件（IOFF），并且确定用于关断finFET器件（VOFF）的电压模型 ）。 该方法还包括将FinFET模型拟合到VOFF。

公开(公告)号：US08806419B2

公开(公告)日：2014-08-12

申请号：US13970806

申请日：2013-08-20

Applicant: International Business Machines Corporation

Inventor： Wilfried Ernest-August Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Hailing Wang ,  Richard Q. Williams

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5009 ,  G06F17/5036

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

Abstract translation: 描述了一种用于对FinFET宽度量化进行建模的方法。 该方法包括将FinFET器件的FinFET模型拟合到单个鳍电流/电压特性。 FinFET器件包括多个翅片。 该方法包括获得至少一个样本FinFET器件的统计数据。 统计数据包括DIBL数据和SS数据。 该方法还包括使用DIBL数据和SS数据将FinFET模型拟合到电流变化以关闭统计数据中的finFET器件（IOFF），并且确定用于关断finFET器件（VOFF）的电压模型 ）。 该方法还包括将FinFET模型拟合到VOFF。

公开(公告)号：US20140217502A1

公开(公告)日：2014-08-07

申请号：US13761476

申请日：2013-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66136 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/938

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.