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    III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
    45.
    发明授权
    III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology 有权
    III-V，SiGe或Ge基极双极晶体管和CMOS混合技术

    公开(公告)号：US09496184B2

    公开(公告)日：2016-11-15

    申请号：US14245627

    申请日：2014-04-04

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L21/8238 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/24 ,  H01L29/10 ,  H01L29/45 ,  H01L29/735 ,  H01L27/06 ,  H01L21/84

    CPC classification number: H01L21/8249 ,  H01L21/244 ,  H01L21/84 ,  H01L27/0623 ,  H01L29/1008 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66545 ,  H01L29/735

    Abstract: In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor. The wafer is doped to form emitter and collector regions on both sides of the dummy gate. A dielectric filler layer is deposited onto the wafer surrounding the dummy gate. The dummy gate is removed selective to the dielectric filler layer, thereby exposing the base. The base is recessed. The base is re-grown from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material. Contacts are formed to the base. Techniques for co-fabricating a bipolar transistor and CMOS FET devices are also provided.

    Abstract translation: 一方面，在晶片上制造双极晶体管器件的方法包括以下步骤。 在晶片上形成虚拟栅极，其中伪栅极存在于作为双极晶体管的基极的晶片的一部分上。 晶圆被掺杂以在虚拟栅极的两侧上形成发射极和集电极区域。 介电填料层沉积在围绕虚拟栅极的晶片上。 对绝缘填料层选择性地去除伪栅极，从而露出基底。 基座凹进。 碱从由SiGe，Ge和III-V材料组成的组中选择的外延材料再生长。 触点形成在基座上。 还提供了用于共同制造双极晶体管和CMOS FET器件的技术。

    Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor
    48.
    发明授权
    Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor 有权
    自对准工艺制造具有周围栅极存取晶体管的存储单元阵列

    公开(公告)号：US08853662B2

    公开(公告)日：2014-10-07

    申请号：US14076267

    申请日：2013-11-11

    Applicant: International Business Machines Corporation

    Inventor： Matthew J. BrightSky ,  Chung H. Lam ,  Gen P. Lauer

    IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2454 ,  H01L45/143 ,  H01L45/144

    Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.

    Abstract translation: 一种包括多个存储单元的存储器阵列。 每个字线电耦合到一组存储器单元，栅极接触和平行于字线定位的一对电介质柱。 绝缘柱放置在栅极接触的两侧。 也是防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括在衬底上形成由绝缘材料制成的一对支柱，在支柱之间和之上沉积导电栅极材料，蚀刻栅极材料，使得其部分地填充在该对柱之间的空间并形成 用于存储单元的字线，以及在介电柱之间沉积栅极接触，使得栅极接触与栅极材料电接触。

    SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
    49.
    发明申请
    SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR 有权
    具有环绕门控存取晶体管的存储器单元阵列的自对准过程

    公开(公告)号：US20140061581A1

    公开(公告)日：2014-03-06

    申请号：US14076267

    申请日：2013-11-11

    Applicant: International Business Machines Corporation

    Inventor： Matthew J. BrightSky ,  Chung H. Lam ,  Gen P. Lauer

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2454 ,  H01L45/143 ,  H01L45/144

    Abstract: A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.

    Abstract translation: 一种包括多个存储单元的存储器阵列。 每个字线电耦合到一组存储器单元，栅极接触和平行于字线定位的一对电介质柱。 绝缘柱放置在栅极接触的两侧。 也是防止栅极接触与衬底上的多个存储器单元的源极接触电连接的方法。 该方法包括在衬底上形成由绝缘材料制成的一对支柱，在支柱之间和之上沉积导电栅极材料，蚀刻栅极材料，使得其部分地填充在该对柱之间的空间并形成 用于存储单元的字线，以及在介电柱之间沉积栅极接触，使得栅极接触与栅极材料电接触。

    Enhanced coercivity in MTJ devices by contact depth control
    50.
    发明授权
    Enhanced coercivity in MTJ devices by contact depth control 有权

    公开(公告)号：US11011698B2

    公开(公告)日：2021-05-18

    申请号：US15487964

    申请日：2017-04-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack

    IPC: H01L27/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

    Abstract: A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness.

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