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    Reconfigurable branch line coupler
    42.
    发明授权
    Reconfigurable branch line coupler 有权
    可重构分支线耦合器

    公开(公告)号：US09466868B2

    公开(公告)日：2016-10-11

    申请号：US14257464

    申请日：2014-04-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hanyi Ding ,  Alberto Valdes Garcia ,  Wayne H. Woods, Jr.

    IPC: H01P5/04 ,  H01P5/22 ,  H01P5/12

    CPC classification number: H01P5/227 ,  H01P5/04

    Abstract: A reconfigurable branch line coupler and methods of designing and reconfiguring the branch line coupler are disclosed. The reconfigurable branch line coupler includes a plurality of transmission lines, each of which comprises a phase shifter. The reconfigurable branch line coupler further includes an input port, which is split into two quadrature signals providing a second and third port between adjacent of the plurality of transmission lines, with a fourth port isolated from the input port at a center frequency.

    Abstract translation: 公开了一种可重新配置的分支线耦合器以及设计和重新配置支线耦合器的方法。 可重新配置的分支线耦合器包括多个传输线，每个传输线包括移相器。 可重构分支线路耦合器还包括输入端口，其被分成两个正交信号，提供在多个传输线路的相邻之间的第二和第三端口，以及以中心频率与输入端口隔离的第四端口。

    On chip bias temperature instability characterization of a semiconductor device
    43.
    发明授权
    On chip bias temperature instability characterization of a semiconductor device 有权
    半导体器件的片上偏置温度不稳定性表征

    公开(公告)号：US09404960B2

    公开(公告)日：2016-08-02

    申请号：US14041422

    申请日：2013-09-30

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  Xuefeng Liu ,  Alvin W. Strong ,  Randy L. Wolf

    IPC: G01R31/26 ,  G01R31/28

    CPC classification number: G01R31/2628 ,  G01R31/2623 ,  G01R31/2822

    Abstract: Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

    Abstract translation: 本发明的实施例提供了表征偏压温度不稳定性对半导体器件的影响的电路和方法。 电路包括具有栅，漏，源和体端子的晶体管。 两个AC焊盘组均具有多个导电焊盘。 两个直流焊盘与直流电源和/或电表通讯。 栅极端子与包括在每个AC焊盘组的多个导电焊盘中的第一导电焊盘连通。 漏极端子与AC焊盘组的第二导电焊盘和源极端子与另一个AC焊盘组的第二导电焊盘连通。 一个直流焊盘通过第一串联电阻器与栅极端子连通，另一个直流焊盘通过第二串联电阻器与主体端子连接，并为栅极和主体端子提供开路。

    Notch filter structure with open stubs in semiconductor substrate and design structure
    44.
    发明授权
    Notch filter structure with open stubs in semiconductor substrate and design structure 有权
    半导体衬底开口短路的陷波滤波器结构和设计结构

    公开(公告)号：US09263782B2

    公开(公告)日：2016-02-16

    申请号：US13748048

    申请日：2013-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Anthony K. Stamper

    IPC: H01P1/203 ,  G06F17/50

    CPC classification number: H01P1/2039 ,  G06F17/5036 ,  G06F17/5045

    Abstract: On-chip millimeter wave (mmW) notch filters with via stubs, methods of manufacture and design structures are disclosed. The notch filter includes a signal line comprising a metal trace line connected to a metal via stub partially extending into a semiconductor substrate. The notch filter further includes a defected ground plane connected to at least one or more additional metal via stubs partially extending into the semiconductor substrate.

    Abstract translation: 公开了具有通孔短片的片上毫米波（mmW）陷波滤波器，制造方法和设计结构。 陷波滤波器包括信号线，该信号线包括连接到部分延伸到半导体衬底中的金属通孔短截线的金属迹线。 陷波滤波器还包括连接到部分延伸到半导体衬底中的经由短截线的至少一个或多个附加金属的缺陷接地平面。

    MILLIMETER WAVE PHASE SHIFTERS USING TUNABLE TRANSMISSION LINES
    46.
    发明申请
    MILLIMETER WAVE PHASE SHIFTERS USING TUNABLE TRANSMISSION LINES 有权
    使用可变传输线的MILLIMETER波形相位切换器

    公开(公告)号：US20150365259A1

    公开(公告)日：2015-12-17

    申请号：US14835286

    申请日：2015-08-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hanyi Ding ,  Alberto Valdes Garcia ,  Wayne H. Woods, JR.

    IPC: H04L25/02 ,  H01P1/18

    CPC classification number: H04L25/0278 ,  G06F17/50 ,  H01P1/182 ,  H01P1/184 ,  H01R43/00 ,  H03K17/687 ,  H04L25/0272

    Abstract: Tunable phase shifters and methods for using the same include a signal line; one or more grounding lines; one or more crossing lines below the signal line in proximity to the signal line and substantially perpendicular to a longitudinal direction of the signal line, where the crossing lines conform to the shape of the signal line along at least three surfaces of the signal line and where the crossing lines have a tunable capacitance; and an inductance return line below the crossing lines substantially parallel to the longitudinal direction of the signal line, where the inductance return line provides a tunable inductance.

    Abstract translation: 可调谐移相器及其使用方法包括信号线; 一条或多条接地线; 信号线下方的一条或多条交叉线，靠近信号线，并且基本上垂直于信号线的纵向方向，其中交叉线沿着信号线的至少三个表面符合信号线的形状，其中 交叉线具有可调电容; 以及在基本上平行于信号线的纵向方向的交叉线下方的电感返回线，其中电感返回线提供可调电感。

    INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH
    47.
    发明申请
    INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH 有权
    通过深度通过硅片进行在线测量

    公开(公告)号：US20150187667A1

    公开(公告)日：2015-07-02

    申请号：US14643436

    申请日：2015-03-10

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  J. Edwin Hostetter ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC: H01L21/66 ,  H01L21/304

    CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

    Abstract translation: 公开了一种通过硅通孔（TSV）电容测试结构和基于电容确定TSV深度的方法。 TSV电容测试结构由均匀间隔的多个TSV条形成。 第一组电杆电连接以形成第一电容器节点，并且第二组电杆电连接以形成第二电容器节点。 测量电容，并在背面变薄之前计算TSV深度。 然后计算的TSV深度可以被馈送到下游研磨和/或抛光工具以控制背面变薄处理，使得半导体晶片变薄使得背面与TSV齐平。

    MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD
    48.
    发明申请
    MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD 有权
    微米波浪水平切片尺寸包装（WLCSP）装置及相关方法

    公开(公告)号：US20150037913A1

    公开(公告)日：2015-02-05

    申请号：US14519590

    申请日：2014-10-21

    Applicant: International Business Machines Corporation

    Inventor： Hanyi Ding ,  Richard S. Graf ,  Gary R. Hill ,  Wayne H. Woods, JR.

    IPC: H01L21/66

    CPC classification number: H01L24/17 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5225 ,  H01L23/66 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/16055 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2924/0002 ,  H01L2924/1532 ,  H01L2924/2076 ,  H01L2924/00

    Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

    Abstract translation: 各种实施例包括晶片级芯片级封装（WLCSP）结构和调谐这种结构的方法。 在一些实施例中，WLCSP结构包括：印刷电路板（PCB）迹线连接，其包括与PCB接地平面连接的至少一个PCB接地连接; 一组接地焊球，每个接触印刷电路板跟踪连接; 与所述一组接地焊球中的所述接地焊球接触的一组芯片焊盘; 连接该组芯片焊盘的芯片接地平面; 以及插入在所述一组接地焊球中的两个之间的信号互连，所述信号互连包括：与所述PCB接地平面电隔离的信号迹线连接; 信号球接触信号PCB跟踪连接; 接触信号球的芯片焊盘和与芯片焊盘接触的芯片上的信号迹线连接。

    HIGH FREQUENCY PHASE SHIFTER ARRAY TESTING
    50.
    发明申请
    HIGH FREQUENCY PHASE SHIFTER ARRAY TESTING 有权
    高频相位阵列测试

    公开(公告)号：US20140203967A1

    公开(公告)日：2014-07-24

    申请号：US13746029

    申请日：2013-01-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Adem G. Aydin ,  Hanyi Ding

    IPC: H01Q3/26

    CPC classification number: H01Q3/267 ,  H01Q3/26

    Abstract: Aspects of the invention provide for an architecture and method for testing high frequency phase shifter arrays. In one embodiment, an architecture for testing a phase shifter array, includes: a plurality of power dividers, each power divider configured to receive an output from a phase shifter within the phase shifter array and split the output into a first signal and a second signal; a plurality of power clippers, each power clipper configured to receive the second signal and modify the second signal by limiting an amplitude of the second signal; a first power combiner configured to receive the first signal from each of the plurality of power dividers to generate a first output; and a second power combiner configured to receive the modified second signal from each of the plurality of power clippers to generate a second output.

    Abstract translation: 本发明的方面提供了用于测试高频移相器阵列的架构和方法。 在一个实施例中，用于测试移相器阵列的架构包括：多个功率分配器，每个功率分配器被配置为从移相器阵列内的移相器接收输出，并将输出分离成第一信号和第二信号 ; 多个功率限幅器，每个功率限幅器被配置为接收第二信号并通过限制第二信号的幅度来修改第二信号; 第一功率组合器，被配置为从所述多个功率分配器中的每一个接收所述第一信号以产生第一输出; 以及第二功率组合器，其被配置为从所述多个功率限幅器中的每一个接收所述经修改的第二信号以产生第二输出。

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