公开(公告)号：US20170243947A1

公开(公告)日：2017-08-24

申请号：US15051973

申请日：2016-02-24

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Hemanth Jagannathan ,  Koichi Motoyama ,  Oscar Van Der Straten

IPC: H01L29/45 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L29/45 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78

Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.

公开(公告)号：US09741812B1

公开(公告)日：2017-08-22

申请号：US15051973

申请日：2016-02-24

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Hemanth Jagannathan ,  Koichi Motoyama ,  Oscar Van Der Straten

IPC: H01L29/45 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L29/45 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78

Abstract: Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact conductor portion comprising a metal having a high resistance to electromigration such as tungsten at a bottom portion of source/drain contact trench to form direct contact with a source/drain region of a field effect transistor, a second contact conductor portion comprising a highly conductive metal such as copper or a copper alloy is formed over the first contact conductor portion.

公开(公告)号：US12167700B2

公开(公告)日：2024-12-10

申请号：US17393847

申请日：2021-08-04

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Joseph F. Maniscalco ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.

公开(公告)号：US12148617B2

公开(公告)日：2024-11-19

申请号：US17453010

申请日：2021-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chanro Park ,  Chi-Chun Liu ,  Stuart Sieg ,  Yann Mignot ,  Koichi Motoyama ,  Hsueh-Chung Chen

IPC: H01L21/033 ,  H01L21/3213

Abstract: A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

公开(公告)号：US12062609B2

公开(公告)日：2024-08-13

申请号：US17453670

申请日：2021-11-05

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Chanro Park ,  Hsueh-Chung Chen ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226

Abstract: Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.

公开(公告)号：US12057395B2

公开(公告)日：2024-08-06

申请号：US17474222

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Chanro Park ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-κ dielectric is formed on the conformal layer such that the low-κ dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-κ dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.

公开(公告)号：US20240213092A1

公开(公告)日：2024-06-27

申请号：US18145157

申请日：2022-12-22

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Scott A. DeVries ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/31144 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53266

Abstract: A chip is manufactured using a method for forming a back-end-of-line (BEOL) layer on an IC chip surface comprises providing a first layer on top of a substrate layer of the IC chip, the first layer comprising a bottom portion of a metallic fill region having a first width as seen in a vertical cross-section of the IC chip. The method further provides a second layer on top of the first layer. The second layer comprises a middle portion of the metallic fill region having a second width that is wider than the bottom portion of the metallic fill region. The method provides a third layer on top of the second layer. The third layer comprises a top portion of the metallic fill region having a third width as seen in the vertical cross-section of the IC chip that is narrower than the middle portion of the metallic fill region.

公开(公告)号：US20240213087A1

公开(公告)日：2024-06-27

申请号：US18146478

申请日：2022-12-27

Applicant: International Business Machines Corporation

Inventor： Oscar van der Straten ,  Koichi Motoyama ,  Willie Lester Muchrison, JR. ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53266

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a first high aspect ratio metal line. The first high aspect ratio metal line includes a first low aspect ratio line segment and a second low aspect ratio line segment.

公开(公告)号：US20240194586A1

公开(公告)日：2024-06-13

申请号：US18078454

申请日：2022-12-09

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Oleg Gluschenkov

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5286

Abstract: A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

公开(公告)号：US20240170532A1

公开(公告)日：2024-05-23

申请号：US18056731

申请日：2022-11-18

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Koichi Motoyama ,  Nicholas Alexander POLOMOFF ,  Leon Sigal

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) comprising a first source/drain (S/D), a second FET comprising a second S/D squarely above the first S/D, and a shared S/D contact. The shared S/D may include a recessed portion between the first S/D and the second S/D, a side portion above the recessed portion, and a top portion above the second S/D. The side portion may contact a lateral side of the second S/D.